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參數(shù)資料
| 型號(hào)： | AD9954/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR 9954 |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | AgileRF™ |
| 主要目的： | 計(jì)時(shí)，直接數(shù)字合成（DDS） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9954 |
| 主要屬性： | 14 位數(shù)模轉(zhuǎn)換器，32 位調(diào)節(jié)字寬 |
| 次要屬性： | 400MHz 圖形用戶界面 |
| 已供物品： | 板，軟件 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD9954YSVZ-REEL7-ND - IC DDS DAC 14BIT 1.8V 48TQFP AD9954YSVZ-ND - IC DDS DAC 14BIT 1.8V 48-TQFP |
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AD9954
Rev. B | Page 23 of 40
Serial I/O Port
The AD9954 serial port is a flexible, synchronous, serial
communications port that easily interfaces to many industry-
standard microcontrollers and microprocessors. The serial I/O port
is compatible with most synchronous transfer formats, including
both the Motorola 6905/11 SPI and Intel 8051 SSR protocols.
The interface accesses all registers that configure the AD9954. MSB
first and LSB first transfer formats are supported. In addition, the
AD9954’s serial interface port can be configured as a single pin I/O
(SDIO), which allows a 2-wire interface, or two unidirectional pins
for in/out (SDIO/SDO), which enables a 3-wire interface. Two
optional pins, IOSYNC and CS, provide further flexibility for
system design with the AD9954.
SERIAL PORT OPERATION
With the AD9954, the instruction byte specifies read/write
operation and register address. Serial operations on the AD9954
only occur at the register level, they do not occur on the byte
level. For the AD9954, the serial port controller recognizes the
instruction byte register address and automatically generates the
proper register byte address. In addition, the controller expects
to access all bytes of that register. It is a requirement that all
bytes of a register be accessed during serial I/O operations, with
one exception; the IOSYNC function can be used to abort an
I/O operation, thereby allowing less than all bytes to be
accessed.
There are two phases to a communication cycle with the
AD9954. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9954, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9954 serial port controller with information regarding
Phase 2, the data transfer cycle. The instruction byte defines
whether the upcoming data transfer is a read or a write and the
serial address of the register being accessed.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9954. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9954
and the system controller. The number of bytes transferred
during Phase 2 of the communication cycle is a function of the
register being accessed. For example, when accessing the Control
Function Register 2, which is three bytes wide, Phase 2 requires that
three bytes be transferred. If accessing the frequency tuning word,
which is four bytes wide, four bytes must be transferred. After
transferring all data bytes per the instruction byte, the
communication cycle is complete.
At the completion of any communication cycle, the AD9954
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle. All
data input to the AD9954 is registered on the rising edge of
SCLK. All data is driven out of the AD9954 on the falling edge
of SCLK. Figure 25 through Figure 28 are provided to aid in
understanding the general operation of the AD9954 serial port.
03
37
4-
00
8
I6
I5
I4
I3
I2
I1
D5
D4
D3
D2
D1
D0
I0
D7
D6
I7
INSTRUCTION CYCLE
SCLK
SDIO
DATA TRANSFER CYCLE
CS
Figure 25. Serial Port Write Timing–Clock Stall Low
03
374
-00
9
I6
I5
I4
I3
I2
I1
I0
DON'T CARE
I7
INSTRUCTION CYCLE
SCLK
SDIO
DATA TRANSFER CYCLE
DO 5 DO 4 DO 3 DO 2 DO 1
DO 0
DO 7 DO 6
SDO
CS
Figure 26. 3-Wire Serial Port Read Timing–Clock Stall Low
03
37
4-
01
0
I6
I5
I4
I3
I2
I1
D5
D4
D3
D2
D1
D0
I0
D7
D6
I7
INSTRUCTION CYCLE
SCLK
SDIO
DATA TRANSFER CYCLE
CS
Figure 27. Serial Port Write Timing–Clock Stall High
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9954YSV | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 400MHz 1-DAC 14-Bit Serial 48-Pin TQFP EP 制造商:Rochester Electronics LLC 功能描述:400 MSPS DDS W/14 BIT DAC - Bulk 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9954 TQFP48 |
| AD9954YSV-REEL7 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9954YSVZ | 功能描述:IC DDS DAC 14BIT 1.8V 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9954YSVZ | 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9954 TQFP48 |
| AD9954YSVZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
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