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參數資料
| 型號： | AD9954/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 14/40頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR 9954 |
| 產品培訓模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標準包裝： | 1 |
| 系列： | AgileRF™ |
| 主要目的： | 計時，直接數字合成（DDS） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9954 |
| 主要屬性： | 14 位數模轉換器，32 位調節(jié)字寬 |
| 次要屬性： | 400MHz 圖形用戶界面 |
| 已供物品： | 板，軟件 |
| 產品目錄頁面： | 552 (CN2011-ZH PDF) |
| 相關產品： | AD9954YSVZ-REEL7-ND - IC DDS DAC 14BIT 1.8V 48TQFP AD9954YSVZ-ND - IC DDS DAC 14BIT 1.8V 48-TQFP |
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AD9954
Rev. B | Page 21 of 40
SYNCHRONIZATION—REGISTER UPDATES (I/O
UPDATE)
Functionality of the SYNC_CLK and I/O UPDATE
Data into the AD9954 is synchronous to the SYNC_CLK
signal (supplied externally to the user on the SYNC_CLK pin).
The I/O UPDATE pin is sampled on the rising edge of the
SYNC_CLK.
Internally, SYSCLK is fed to a divide-by-four frequency divider
to produce the SYNC_CLK signal. The SYNC_CLK signal is
made available to the system on the SYNC_CLK pin. This
enables synchronization of external hardware with the device’s
internal clocks. This is accomplished by providing the SYNC_CLK
signal as an output that external hardware can then use to
synchronize against.
The I/O update signal coupled with SYNC_CLK is used to
transfer internal buffer contents into the control registers. The
combination of the SYNC_CLK pin and the I/O UPDATE pin
provides the user with constant latency relative to SYSCLK and
ensures phase continuity of the analog output signal when a
new tuning word or phase offset value is asserted.
Figure 23 and Figure 24 demonstrate an I/O update timing
cycle and synchronization.
Synchronization logic notes include the following:
The I/O update signal is edge detected to generate a single-
cycle clock signal that drives the register bank flops. The I/O
update signal has no constraints on duty cycle. The minimum
low time on I/O update is one SYNC_CLK clock cycle.
The I/O UPDATE pin is set up and held around the rising
edge of SYNC_CLK. Setup and hold time specifications can
be found in Table 2.
03
37
4-
0
6
SYSCLK
SDIO
SYNC_CLK
DISABLE
10
0
SCLK
TO CORE LOGIC
CS
OSK
D
Q
PS<1:0>
D
Q
I/O UPDATE
D
Q
÷4
SYNC_CLK
GATING
EDGE
DETECTION
LOGIC
REGISTER
MEMORY
I/O BUFFER
LATCHES
Figure 23. I/O Synchronization Block Diagram
SYNC_CLK
SYSCLK
AB
DATA IN
REGISTERS
DATA IN
I/O BUFFERS
I/O UPDATE
THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM
THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B.
0
33
74
-0
07
N – 1
N
N + 1
N
N + 1
N + 2
Figure 24. I/O Synchronization Timing Diagram
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9954YSV | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 400MHz 1-DAC 14-Bit Serial 48-Pin TQFP EP 制造商:Rochester Electronics LLC 功能描述:400 MSPS DDS W/14 BIT DAC - Bulk 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9954 TQFP48 |
| AD9954YSV-REEL7 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9954YSVZ | 功能描述:IC DDS DAC 14BIT 1.8V 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9954YSVZ | 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9954 TQFP48 |
| AD9954YSVZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
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