參數(shù)資料
型號(hào)： AD9954/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/40頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR 9954
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 1
系列： AgileRF™
主要目的： 計(jì)時(shí)，直接數(shù)字合成（DDS）
嵌入式： 否
已用 IC / 零件： AD9954
主要屬性： 14 位數(shù)模轉(zhuǎn)換器，32 位調(diào)節(jié)字寬
次要屬性： 400MHz 圖形用戶界面
已供物品： 板，軟件
產(chǎn)品目錄頁(yè)面： 552 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： AD9954YSVZ-REEL7-ND - IC DDS DAC 14BIT 1.8V 48TQFP
AD9954YSVZ-ND - IC DDS DAC 14BIT 1.8V 48-TQFP
AD9954
Rev. B | Page 19 of 40
03
37
4-
00
3
FTW0
SINGLE-TONE
MODE
LINEAR SWEEP MODE
AT POINT A: LOAD RISING RAMP RATE REGISTER, APPLY RISING DFTW.
AT POINT B: LOAD FALLING RAMP RATE REGISTER, APPLY FALLING DFTW.
PS<0> = 1
PS<0>= 0
PS<0> =0
TIME
FTW1
A
B
fOUT
Figure 21. Linear Sweep Frequency Plan
03
37
4-
00
4
FTW0
SINGLE-TONE
MODE
LINEAR SWEEP MODE ENABLE–NO DWELL BIT SET
FTW1
AA
A
B
BB
fOUT
TIME
PS<0> = 1 PS<0> = 0
PS<0> = 0
PS<0> = 1
PS<0> = 0
Figure 22. Linear Sweep Using No-Dwell Frequency Plan
Linear Sweep No-Dwell Feature
See CFR1<2> in the register maps (see Table 12 and Table 13)
for general details of the no-dwell mode. Figure 22 depicts the
linear sweep mode operation when the linear sweep no-dwell
bit is set. The Label A points indicate where a rising edge on
PS0 is detected; the Label B points indicate where the AD9954
has determined fOUT has reached the terminal frequency and
automatically returns to the starting frequency. Note that in this
mode, only sweeps from FTW0 to FTW1 using the positive
linear sweep control word are supported. Toggling PS0 from 1
to 0 neither initiates a falling sweep when the no-dwell bit is set,
nor interrupts a positive sweep already underway.
Resetting the Ramp Rate Timer
The ramp timer can be reset before reaching a count of 1 by
three methods.
Method one is by changing the PS0 input pin. When the PS0
input pin toggles from 0 to 1, the RSRRW value is loaded into
the ramp rate timer, which then proceeds to countdown as
normal. When the PS0 input pin toggles from 0 to 1, the falling
sweep ramp rate word (FSRRW) value is loaded into the ramp
rate timer, which then proceeds to countdown as normal.
The second method uses the LOAD SRR @ I/O UD bit
(CFR1<15>), see Table 12 for details.
相關(guān)PDF資料
PDF描述
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381A303-71-0 BOOT MOLDED
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9954YSV 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 400MHz 1-DAC 14-Bit Serial 48-Pin TQFP EP 制造商:Rochester Electronics LLC 功能描述:400 MSPS DDS W/14 BIT DAC - Bulk 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9954 TQFP48
AD9954YSV-REEL7 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
AD9954YSVZ 功能描述:IC DDS DAC 14BIT 1.8V 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9954YSVZ 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9954 TQFP48
AD9954YSVZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer
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