CL = 20 pF, f" />
參數(shù)資料
型號(hào): AD9949KCPZRL
廠商: Analog Devices Inc
文件頁數(shù): 32/36頁
文件大?。?/td> 0K
描述: IC CCD SIGNAL PROCESSOR 40-LFCSP
標(biāo)準(zhǔn)包裝: 2,500
類型: CCD 信號(hào)處理器,12 位
輸入類型: 邏輯
輸出類型: 邏輯
接口: 3 線串口
安裝類型: 表面貼裝
封裝/外殼: 40-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 40-LFCSP
包裝: 帶卷 (TR)
AD9949
Rev. B | Page 5 of 36
TIMING SPECIFICATIONS
CL = 20 pF, fCLI = 36 MHz, unless otherwise noted.
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
MASTER CLOCK (CLI) (See Figure 16)
CLI Clock Period
tCLI
27.8
ns
CLI High/Low Pulse Width
tADC
11.2
13.9
16.6
ns
Delay from CLI to Internal Pixel Period Position
tCLIDLY
6
ns
CLPOB PULSE WIDTH (PROGRAMMABLE)1
tCOB
2
20
Pixels
SAMPLE CLOCKS (See Figure 18)
SHP Rising Edge to SHD Rising Edge
tS1
12.5
13.9
ns
DATA OUTPUTS (See Figure 19 and Figure 20)
Output Delay From Programmed Edge
tOD
6
ns
Pipeline Delay
11
Cycles
SERIAL INTERFACE (SERIAL TIMING SHOWN IN Figure 14 and Figure 15)
Maximum SCK Frequency
fSCLK
10
MHz
SL to SCK Setup Time
tLS
10
ns
SCK to SL Hold Time
tLH
10
ns
SDATA Valid to SCK Rising Edge Setup
tDS
10
ns
SCK Falling Edge to SDATA Valid Hold
tDH
10
ns
SCK Falling Edge to SDATA Valid Read
tDV
10
ns
1 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
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