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參數(shù)資料
| 型號： | AD9949KCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 40-LFCSP |
| 標準包裝： | 2,500 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP |
| 包裝： | 帶卷 (TR) |
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AD9949
Rev. B | Page 18 of 36
PRECISION TIMING HIGH SPEED TIMING GENERATION
The AD9949 generates flexible high speed timing signals using
the Precision Timing core. This core is the foundation for gener-
ating the timing used for both the CCD and the AFE: the reset
gate (RG), horizontal drivers (H1 to H4), and the SHP/SHD
sample clocks. A unique architecture makes it routine for the
system designer to optimize image quality by providing precise
control over the horizontal CCD readout and the AFE corre-
lated double sampling.
TIMING RESOLUTION
The Precision Timing core uses a 1× master clock input (CLI) as
a reference. This clock should be the same as the CCD pixel
clock frequency. Figure 16 illustrates how the internal timing
core divides the master clock period into 48 steps or edge
positions. Therefore, the edge resolution of the Precision Timing
core is (tCLI/48). For more information on using the CLI input,
refer to the Applications Information section.
HIGH SPEED CLOCK PROGRAMMABILITY
Figure 17 shows how the high speed clocks, RG, H1 to H4,
SHP, and SHD, are generated. The RG pulse has programma-
ble rising and falling edges and may be inverted using the
polarity control. The horizontal clocks H1 and H3 have
programmable rising and falling edges and polarity control.
The H2 and H4 clocks are always inverses of H1 and H3, re-
spectively. Table 16 summarizes the high speed timing registers
and their parameters.
Each edge location setting is 6 bits wide, but only 48 valid edge
locations are available. Therefore, the register values are
mapped into four quadrants, with each quadrant containing
12 edge locations. Table 17 shows the correct register values for
the corresponding edge locations.
NOTES
1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (
tCLIDLY = 6 ns TYP).
P[0]
P[48] = P[0]
P[12]
P[24]
P[36]
1 PIXEL
PERIOD
...
CLI
tCLIDLY
POSITION
03751-017
Figure 16. High Speed Clock Resolution from CLI Master Clock Input
H1/H3
H2/H4
CCD SIGNAL
RG
12
3
4
56
PROGRAMMABLE CLOCK POSITIONS:
1. RG RISING EDGE.
2. RG FALLING EDGE.
3. SHP SAMPLE LOCATION.
4. SHD SAMPLE LOCATION.
5. H1/H3 RISING EDGE POSITION6. H1/H3 FALLING EDGE POSITION (H2/H4 ARE INVERSE OF H1/H3).
03751-018
Figure 17. High Speed Clock Programmable Locations
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