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參數(shù)資料
| 型號： | AD9948KCPZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 10-Bit CCD Signal Processor with Precision Timing⑩ Core |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, MO-220-VJJD-2, LFCSP-40 |
| 文件頁數(shù)： | 19/28頁 |
| 文件大?。?/td> | 436K |
| 代理商： | AD9948KCPZRL |
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REV. 0
AD9948
–19–
POWER-UP PROCEDURE
VDD
(INPUT)
SERIAL
WRITES
VD
(OUTPUT)
1 H
ODD FIELD
EVEN FIELD
...
...
DIGITAL
OUTPUTS
CLOCKS ACTIVE WHEN OUT_CONTROL REGISTER IS
UPDATED AT VD/HD EDGE
H1/H3, RG
H2/H4
t
PWR
CLI
(INPUT)
HD
(OUTPUT)
1V
...
...
Figure 14. Recommended Power-Up Sequence
Recommended Power-Up Sequence
When the AD9948 is powered up, the following sequence is
recommended (refer to Figure 14 for each step):
1. Turn on the power supplies for the AD9948.
2. Apply the master clock input, CLI, VD, and HD.
3. Although the AD9948 contains an on-chip power-on reset, a
software reset of the internal registers is recommended. Write
a 1 to the SW_RST register (Address x010), which will reset
all the internal registers to their default values. This bit is
self-clearing and will automatically be reset back to 0.
4. The Precision Timing core must be reset by writing a 0 to the
TGCORE_RSTB register (Address x012) followed by writing
a l to the TGCORE_RSTB register. This will start the internal
timing core operation.
5. Write a 1 to the PREVENTUPDATE register (Address x014).
This will prevent the updating of the serial register data.
6. Write to the desired registers to configure high speed timing
and horizontal timing.
7. Write a 1 to the OUT_CONTROL register (Address x011).
This will allow the outputs to become active after the next
VD/HD rising edge.
8. Write a 0 to the PREVENTUPDATE register (Address x014).
This will allow the serial information to be updated at next
VD/HD falling edge.
The next VD/HD falling edge allows register updates to occur,
including OUT_CONTROL, which enables all clock outputs.
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