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參數(shù)資料
| 型號(hào)： | AD9948KCPZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | 10-Bit CCD Signal Processor with Precision Timing⑩ Core |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, MO-220-VJJD-2, LFCSP-40 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 436K |
| 代理商： | AD9948KCPZRL |
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REV. 0
–14–
AD9948
PRECISION TIMING HIGH SPEED TIMING GENERATION
The AD9948 generates flexible high speed timing signals using
the Precision Timing core. This core is the foundation for gener-
ating the timing used for both the CCD and the AFE; the reset
gate RG, horizontal drivers H1–H4, and the SHP/SHD sample
clocks. A unique architecture makes it routine for the system
designer to optimize image quality by providing precise control
over the horizontal CCD readout and the AFE correlated
double sampling.
Timing Resolution
The Precision Timing core uses a 1
×
master clock input (CLI)
as a reference. This clock should be the same as the CCD pixel
clock frequency. Figure 4 illustrates how the internal timing core
divides the master clock period into 48 steps or edge positions.
Therefore, the edge resolution of the Precision Timing core is
(t
CLI
/48). For more information on using the CLI input, refer to
the Applications Information section.
High Speed Clock Programmability
Figure 5 shows how the high speed clocks, RG, H1–H4, SHP,
and SHD, are generated. The RG pulse has programmable rising
and falling edges, and may be inverted using the polarity control.
The horizontal clocks H1 and H3 have programmable rising and
falling edges, and polarity control. The H2 and H4 clocks are
always inverses of H1 and H3, respectively. Table X summarizes
the high speed timing registers and their parameters.
Each edge location setting is 6 bits wide, but only 48 valid edge
locations are available. Therefore, the register values are mapped
into four quadrants, with each quadrant containing 12 edge
locations. Table XI shows the correct register values for the
corresponding edge locations.
NOTES
1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (
t
CLIDLY
= 6 ns TYP).
P[0]
P[48] = P[0]
P[12]
P[24]
P[36]
1 PIXEL
PERIOD
...
...
CLI
t
CLIDLY
POSITION
Figure 4. High Speed Clock Resolution From CLI Master Clock Input
H1/H3
H2/H4
CCD SIGNAL
RG
(1)
(2)
(3)
(4)
(5)
(6)
PROGRAMMABLE CLOCK POSITIONS:
1. RG RISING EDGE
2. RG FALLING EDGE
3. SHP SAMPLE LOCATION
4. SHD SAMPLE LOCATION
5. H1/H3 RISING EDGE POSITION
6. H1/H3 FALLING EDGE POSITION (H2/H4 ARE INVERSE OF H1/H3)
Figure 5. High Speed Clock Programmable Locations
Table X. H1CONTROL, RGCONTROL, DRVCONTROL, and SAMPCONTROL Register Parameters
Parameter
Length
Range
Description
Polarity
Positive Edge
Negative Edge
Sample Location
Drive Control
DOUT Phase
1b
6b
6b
6b
3b
6b
High/Low
0–47 Edge Location
0–47 Edge Location
0–47 Sample Location
0–7 Current Steps
0–47 Edge Location
Polarity Control for H1/H3 and RG (0 = No Inversion, 1 = Inversion).
Positive Edge Location for H1/H3 and RG.
Negative Edge Location for H1/H3 and RG.
Sampling Location for SHP and SHD.
Drive Current for H1–H4 and RG Outputs, 0–7 Steps of 4.1 mA Each.
Phase Location of Data Outputs with Respect to Pixel Period.
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