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參數(shù)資料
| 型號(hào)： | AD9948KCPZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | 10-Bit CCD Signal Processor with Precision Timing⑩ Core |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, MO-220-VJJD-2, LFCSP-40 |
| 文件頁(yè)數(shù)： | 18/28頁(yè) |
| 文件大?。?/td> | 436K |
| 代理商： | AD9948KCPZRL |
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REV. 0
–18–
AD9948
UP TO FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE
PROGRAMMED WITHIN A SINGLE FIELD, USING THE SEQUENCE CHANGE POSITIONS.
SEQUENCE CHANGE OF POSITION 1
SEQUENCE CHANGE OF POSITION 2
SEQUENCE CHANGE OF POSITION 3
SINGLE FIELD (1 VD INTERVAL)
CLAMP AND PBLK SEQUENCE REGION 0
SEQUENCE CHANGE OF POSITION 0
(V-COUNTER = 0)
CLAMP AND PBLK SEQUENCE REGION 3
CLAMP AND PBLK SEQUENCE REGION 2
CLAMP AND PBLK SEQUENCE REGION 1
Figure 12. Clamp and Blanking Sequence Flexibility
Table XV. External HBLK Register Parameters
Register
Length
Range
Description
HBLKDIR
1b
High/Low
Specifies HBLK Internally Generated or Externally Supplied.
1 = External.
External HBLK Active Polarity.
0 = Active Low.
1 = Active High.
External HBLK Masking Polarity.
0 = Mask H1 Low.
1 = Mask H1 High.
HBLKPOL
1b
High/Low
HBLKEXTMASK
1b
High/Low
0
0
0
1
1
2
1
1
1
0
0
3
1
1
0
0
0
1
2
3
4
5
6
7
8
9
10
11
12
14
15
0
1
2
3
0
2
3
H-COUNTER
RESET
VD
NOTES
1. INTERNAL H-COUNTER IS RESET SEVEN CLI CYCLES AFTER THE HD FALLING EDGE (WHEN USING VDHDEDGE = 0).
2. TYPICAL TIMING RELATIONSHIP: CLI RISING EDGE COINCIDES WITH HD FALLING EDGE.
3. PxGA STEERING IS SYNCHRONIZED WITH THE RESET OF THE INTERNAL H-COUNTER (MOSAIC SEPARATE MODE IS SHOWN).
HD
X
X
X
X
X
X
X
PxGA GAIN
REGISTER
CLI
X
X
X
X
X
X
X
H-COUNTER
(PIXEL COUNTER)
X
X
X
X
X
X
Figure 13. H-Counter Synchronization
H-COUNTER SYNCHRONIZATION
The H-Counter reset occurs seven CLI cycles following the HD
falling edge. The PxGA steering is synchronized with the reset
of the internal H-Counter (see Figure 13).
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