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參數(shù)資料
| 型號： | AD9948KCPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 10-Bit CCD Signal Processor with Precision Timing⑩ Core |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC40 |
| 封裝： | 6 X 6 MM, MO-220-VJJD-2, LFCSP-40 |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 436K |
| 代理商： | AD9948KCPZ |
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REV. 0
AD9948
–9–
SERIAL INTERFACE TIMING
All of the internal registers of the AD9948 are accessed through
a 3-wire serial interface. Each register consists of an 8-bit address
and a 24-bit data-word. Both the 8-bit address and 24-bit data-
word are written starting with the LSB. To write to each register,
a 32-bit operation is required, as shown in Figure 3a. Although
many registers are less than 24 bits wide, all 24 bits must be
written for each register. If the register is only 16 bits wide, then
the upper eight bits are don’t cares and may be filled with zeros
during the serial write operation. If fewer than 24 bits are written,
the register will not be updated with new data.
Figure 3b shows a more efficient way to write to the registers by
using the AD9948’s address auto-increment capability. Using
this method, the lowest desired address is written first, followed
by multiple 24-bit data-words. Each new 24-bit data-word will
be written automatically to the next highest register address. By
eliminating the need to write each 8-bit address, faster register
loading is achieved. Address auto-increment may be used start-
ing with any register location, and may be used to write to as
few as two registers or as many as the entire register space.
COMPLETE REGISTER LISTING
All addresses and default values are expressed in hexadecimal.
All registers are VD/HD updated as shown in Figure 3a, except
for the registers indicated in Table I, which are SL updated.
Table I. SL-Updated Registers
Register
Description
OPRMODE
CTLMODE
SW_RESET
TGCORE _RSTB
PREVENTUPDATE
VDHDEDGE
FIELDVAL
HBLKRETIME
CLPBLKOUT
CLPBLKEN
H1CONTROL
RGCONTROL
DRVCONTROL
SAMPCONTROL
DOUTPHASE
AFE Operation Modes
AFE Control Modes
Software Reset Bit
Reset Bar Signal for Internal TG Core
Prevents Update of Registers
VD/HD Active Edge
Resets Internal Field Pulse
Retimes the HBLK to Internal Clock
CLP/BLK Output Pin Select
Enables CLP/BLK Output Pin
H1/H2 Polarity Control
H1 Positive Edge Location
H1 Negative Edge Location
H1 Drive Current
H2 Drive Current
SDATA
A0
A1
A2
A4
A5
A6
A7
D0
D1
D2
D3
D21
D22
D23
SCK
SL
A3
NOTES
1. INDIVIDUAL SDATA BITS ARE LATCHED ON SCK RISING EDGES.
2. ALL 32 BITS MUST BE WRITTEN: 8 BITS FOR ADDRESS AND 24 BITS FOR DATA.
3. IF THE REGISTER LENGTH IS <24 BITS, THEN DON’T CARE BITS MUST BE USED TO COMPLETE THE 24-BIT DATA LENGTH.
4. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
5. VD/HD UPDATE POSITION MAY BE DELAYED TO ANY HD FALLING EDGE IN THE FIELD USING THE UPDATE REGISTER.
t
DH
t
LS
t
LH
t
DS
VD
SL UPDATED
VD/HD UPDATED
HD
...
...
...
...
...
8-BIT ADDRESS
24-BIT DATA
1
32
2
3
4
5
6
7
8
9
10
11
12
30
31
Figure 3a. Serial Write Operation
SDATA
A0
A1
A2
A4
A5
A6
A7
D0
D1
D22
D23
SCK
SL
A3
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 24-BIT DATA-WORDS.
3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 24-BIT DATA-WORD (ALL 24 BITS MUST BE WRITTEN).
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
D0
D1
D22
D23
D0
...
...
...
DATA FOR STARTING
REGISTER ADDRESS
...
DATA FOR NEXT
REGISTER ADDRESS
D2
D1
...
...
...
...
1
32
2
3
4
5
6
7
8
9
10
31
34
33
56
55
58
57
59
Figure 3b. Continuous Serial Write Operation
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