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| 型號： | AD9911BCPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 500 MSPS Direct Digital Synthesizer with 10-Bit DAC |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 10-BIT DAC, QCC56 |
| 封裝： | 8 X 8 MM, LEAD FREE, MO-220VLLD-2, LFCSP-56 |
| 文件頁數(shù)： | 10/44頁 |
| 文件大?。?/td> | 666K |
| 代理商： | AD9911BCPZ |
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AD9911
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 10 of 44
PIN 1
INDICATOR
NC = NO CONNECT
1
2
3
4
5
6
7
8
9
SYNC_IN
SYNC_OUT
PWR_DWN_CTL
AVDD
NC
AVDD
AVDD
AVDD
NC
AVDD
AVNC
AVDD
10
11
12
13
14
35
34
AGND
33
AVDD
32
NC
31
30
AVDD
29
AVDD
36
IOUT
37
38
AVDD
39
40
AVDD
41
42
P1
1
A
1
N
1
D
1
A
2
A
2
A
2
R
2
R
2
C
2
A
2
A
2
L
2
N
1
A
4
4
4
4
4
5
5
5
5
5
4
4
TOP VIEW
(Not to Scale)
AD9911
5
5
NOTES
1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS
AN ELECTRICAL CONNECTION AND MUST BE
SOLDERED TO GROUND.
2. PIN 49 IS DVDD_I/O AND IS TIED TO 3.3V.
Figure 6. Pin Configuration
0
Table 3. Pin Function Descriptions
Pin No.
1
Mnemonic
SYNC_IN
I/O
I
Description
Synchronizes Multiple AD9911 Devices. Connects to the SYNC_OUT pin of the master
AD9911 device.
Synchronizes Multiple AD9911 Devices. Connects to the SYNC_IN pin of the slave
AD9911 device.
Active High Reset Pin. Asserting this pin forces the internal registers to the default
state shown in the Register Map section.
External Power-Down Control. See the Power Down Functions section for details.
Analog Power Supply Pins (1.8 V).
2
SYNC_OUT
O
3
MASTER_RESET
I
4
5, 7, 8, 9, 11, 13, 14,
15, 19, 21, 26, 29,
30, 31, 33, 37, 39
18, 20, 25, 34, 38
45, 55
44, 56
35
36
17
PWR_DWN_CTL
AVDD
I
I
AGND
DVDD
DGND
IOUT
IOUT
DAC_RSET
I
I
I
O
O
I
Analog Ground Pins.
Digital Power Supply Pins (1.8 V).
Digital Power Ground Pins.
Complementary DAC Output. Terminates into AVDD.
True DAC Output. Terminates into AVDD.
Establishes the Reference Current for the DAC. A 1.91 kΩ resistor (nominal) is
connected from Pin 17 to AGND.
Complementary Reference Clock/Oscillator Input. When the REF_CLK is operated in
single-ended mode, this pin should be decoupled to AVDD or AGND with a
0.1 μF capacitor.
Reference Clock/Oscillator Input. When the REF_CLK operates in single-ended mode,
Pin 23 is the input. See the Modes of Operation section for the reference clock
configuration.
Control Pin for the Oscillator. CAUTION: Do not drive this pin beyond 1.8 V. When high
(1.8 V), the oscillator is enabled to accept a crystal as the REF_CLK source. When low,
the oscillator is bypassed.
Connects to the External Zero Compensation Network of the PLL Loop Filter. Typically,
the network consists of a 0 Ω resistor in series with a 680 pF capacitor tied to AVDD.
22
REF_CLK
I
23
REF_CLK
I
24
CLK_MODE_SEL
I
27
LOOP_FILTER
I
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| AD9911BCPZ-REEL7 | 功能描述:IC DDS 500MSPS DAC 10BIT 56LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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