參數(shù)資料
型號: AD9891KBC
廠商: ANALOG DEVICES INC
元件分類: 消費家電
英文描述: CCD Signal Processors with Precision Timing⑩ Generator
中文描述: SPECIALTY CONSUMER CIRCUIT, PBGA64
封裝: PLASTIC, CSPBGA-64
文件頁數(shù): 31/59頁
文件大?。?/td> 599K
代理商: AD9891KBC
REV. A
AD9891/AD9895
–31–
R
R
Gb
Gb
Gr
Gr
B
B
CCD: PROGRESSIVE BAYER
LINE0
GAIN0, GAIN1, GAIN0, GAIN1, ...
R
R
Gr
Gr
Gb
Gb
B
B
LINE1
LINE2
GAIN2, GAIN3, GAIN2, GAIN3, ...
GAIN0, GAIN1, GAIN0, GAIN1, ...
MOSAIC SEPARATE COLOR
STEERING MODE
Figure 38a. CCD Color Filter Example: Progressive Scan
LINE0
GAIN0, GAIN1, GAIN0, GAIN1, ...
R
R
Gr
Gr
LINE1
LINE2
GAIN0, GAIN1, GAIN0, GAIN1, ...
GAIN0, GAIN1, GAIN0, GAIN1, ...
Gb
Gb
B
B
LINE0
GAIN2, GAIN3, GAIN2, GAIN3, ...
LINE1
LINE2
GAIN2, GAIN3, GAIN2, GAIN3, ...
GAIN2, GAIN3, GAIN2, GAIN3, ...
MOSAIC INTERLACED
COLOR STEERING MODE
Gb
Gb
B
B
Gb
Gb
B
B
Gb
Gb
B
B
R
R
Gr
Gr
R
R
Gr
Gr
R
R
Gr
Gr
EVEN FIELD
ODD FIELD
CCD: INTERLACED BAYER
Figure 38b. CCD Color Filter Example: Interlaced
VD
NOTES
1. VD FALLING EDGE WILL RESET THE
PxGA
GAIN REGISTER STEERING TO “0101” LINE.
2. HD FALLING EDGES WILL ALTERNATE THE
PxGA
GAIN REGISTER STEERING BETWEEN “0101” AND “2323” LINES.
3. FLD STATUS IS IGNORED.
HD
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
2
3
3
2
2
3
3
X
X
REGISTER
GAIN
FLD
ODD FIELD
EVEN FIELD
Figure 39a. Mosaic Separate Color Steering Mode
VD
NOTES
1. FLD FALLING EDGE (START OF ODD FIELD) WILL RESET THE
PxGA
GAIN REGISTER STEERING TO “0101” LINE.
2. FLD RISING EDGE (START OF EVEN FIELD) WILL RESET THE
PxGA
GAIN REGISTER STEERING TO “2323” LINE.
3. HD FALLING EDGES WILL RESET THE
PxGA
GAIN REGISTER STEERING TO EITHER “0” (FLD = ODD) OR “2” (FLD = EVEN).
HD
0
0
0
0
2
2
2
0
2
1
1
1
1
3
3
3
3
0
0
1
1
2
2
3
3
X
X
PxGA
GAIN
REGISTER
FLD
ODD FIELD
EVEN FIELD
Figure 39b. Mosaic Interlaced Color Steering Mode
example, the Mosaic Separate Steering Mode accommodates the
popular
Bayer
arrangement of Red, Green, and Blue filters
(see Figure 38a).
The same Bayer pattern can also be interlaced, and the Mosaic
Interlaced Mode should be used with this type of CCD (see
Figure 38b). The color steering performs the proper multiplex-
ing of the R, G, and B gain values (loaded into the
PxGA
gain
registers) and is synchronized by the vertical (VD) and horizon-
tal (HD) sync pulses. The
PxGA
gain for each of the four
channels is variable from
2 dB to +10 dB, controlled in 64
steps through the serial interface. The
PxGA
gain curve is
shown in Figure 40.
COLOR
STEERING
CONTROL
4:1
MUX
3
PxGA
STEERING
MODE
SELECTION
2
6
VD
HD
GAIN
PxGA
CONTROL
REGISTER
BITS D0:D2
SHP/SHD
VGA
CDS
GAIN0
GAIN1
GAIN2
GAIN3
PxGA
Figure 37. PxGA Block Diagram
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