參數(shù)資料
型號: AD9891KBC
廠商: ANALOG DEVICES INC
元件分類: 消費家電
英文描述: CCD Signal Processors with Precision Timing⑩ Generator
中文描述: SPECIALTY CONSUMER CIRCUIT, PBGA64
封裝: PLASTIC, CSPBGA-64
文件頁數(shù): 16/59頁
文件大?。?/td> 599K
代理商: AD9891KBC
REV. A
–16–
AD9891/AD9895
Table III. CLPOB, CLPDM, and PBLK Individual Sequence Parameters
Register
SPOL
TOG1
TOG2
Length
1b
12b
12b
Range
High/Low
0
4095 Pixel Location
0
4095 Pixel Location
Description
Starting Polarity of Vertical Transfer Pulse for Sequences 0
3
First Toggle Position within Line for Sequences 0
3
Second Toggle Position within Line for Sequences 0
3
Table IV. HBLK Individual Sequence Parameters
Register
HBLKMASK
HBLKTOG1
HBLKTOG2
Length
1b
12b
12b
Range
High/Low
0
4095 Pixel Location
0
4095 Pixel Location
Description
Masking Polarity for H1 for Sequences 0
3 (0 = H1 Low, 1 = H1 High)
First Toggle Position within Line for Sequences 0
3
Second Toggle Position within Line for Sequences 0
3
Table V. Horizontal Sequence Control Parameters for CLPOB, CLPDM, and PBLK
Register
SCP1
SCP3
SPTR0
SPTR3
Length
12b
2b
Range
0
4095 Line Number
0
3 Sequence Number
Description
CLPOB/PBLK SCP to Define Horizontal Regions 0
3
Sequence Pointer for Horizontal Regions 0
3
Table VI. Horizontal Sequence Control Parameters for HBLK
Register
VTPRCP1
VTPRCP7
HBLKSPTR0
HBLKSPTR7
Length
12b
Range
0
4095 Line Number
Description
Vertical Region Change Positions (See Table IX.)
2b
0
3 Sequence Number
Sequence Pointer for HBLK Regions 0
7
UP TO FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE PROGRAMMED WITH-
IN A SINGLE FIELD, USING THE SEQUENCE CHANGE POSITIONS.
SEQUENCE CHANGE POSITION #1
SEQUENCE CHANGE POSITION #2
SEQUENCE CHANGE POSITION #3
SINGLE FIELD (1 VD INTERVAL)
CLAMP AND PBLK SEQUENCE REGION 1
SEQUENCE CHANGE POSITION #0
(V-COUNTER = 0)
CLAMP AND PBLK SEQUENCE REGION 4
CLAMP AND PBLK SEQUENCE REGION 3
CLAMP AND PBLK SEQUENCE REGION 2
Figure 16. Clamp and Blanking Sequence Flexibility
zontal
sequences. Up to four SCPs are available to divide the
readout into four separate regions, as shown in Figure 16. The
SCP0 is always hard-coded to line 0, and SCP1
SCP3 are
register programmable. During each region bound by the SCP,
the
SPTR Registers designate which sequence is used by each
signal.
CLPOB and CLPDM share the same SCP, PBLK has a
separate
set of SCP, and HBLK shares the vertical RCP (see
Vertical Timing Generation section). For example,
CLPSCP1 will define Region 0 for CLPOB and CLPDM,
and in that region
any of the four individual
CLPOB and
CLPDM sequences may be selected with the
SPTR Registers.
The next SCP defines a new
region, and in that region each
signal can be assigned to a different individual sequence. Be-
cause HBLK shares the vertical RCP, there are up to eight
regions where HBLK sequences may be changed using the eight
HBLKSPTR Registers.
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