- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375249 > AD9891KBC (ANALOG DEVICES INC) CCD Signal Processors with Precision Timing⑩ Generator PDF資料下載
參數(shù)資料
| 型號： | AD9891KBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processors with Precision Timing⑩ Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA64 |
| 封裝： | PLASTIC, CSPBGA-64 |
| 文件頁數(shù)： | 30/59頁 |
| 文件大?。?/td> | 599K |
| 代理商： | AD9891KBC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁
REV. A
–30–
AD9891/AD9895
ANALOG FRONT END DESCRIPTION AND OPERATION
The AD9891/AD9895 AFE signal processing chain is shown in
Figure 36. Each processing step is essential in achieving a high
quality image from the raw CCD pixel data. AFE Register de-
tails are shown in Table XXXI.
DC Restore
To reduce the large dc offset of the CCD output signal, a dc-
restore circuit is used with an external 0.1
μ
F series coupling
capacitor. This restores the dc level of the CCD signal to
approximately 1.5 V, to be compatible with the 3 V analog
supply of the AD9891/AD9895.
Correlated Double Sampler
The CDS circuit samples each CCD pixel twice to extract the
video
information and reject low frequency noise. The tim
ing
shown in Figure 10 illustrates how the two internally
generated CDS clocks, SHP and SHD, are used to sample
the reference level and the data level, respectively, of the
CCD signal. The placement of the SHP and SHD sampling
edges is determined by the setting of the SHPPOSLOC and
SHDPOSLOC Registers located at Addr 0xE9 and
Addr 0xEA,
respectively. Placement of these two clock signals
is critical in achieving the best performance from the CCD.
Input Clamp
A line-rate input clamping circuit is used to remove the CCD
’
s
optical black offset. This offset exists in the CCD
’
s shielded
black reference pixels. The AD9891/AD9895 remove this offset
in the
input stage to minimize the effect of a gain change on the
system
black level. Another advantage
of removing this offset at
the input stage is to maximize system
headroom. Some area
CCDs have large black level offset voltages,
which, if not cor-
rected at the input stage, can significantly reduce
the available
headroom in the internal circuitry when higher VGA
gain set-
tings are used.
The input clamp is controlled by the CLPDM signal, which is
fully programmable (see Horizontal Clamping and Blanking
section).
System timing examples are shown in the Horizontal
Timing Sequence Example
section. It is recommended that the
CLPDM pulse be used during
valid CCD dark pixels. CLPDM
may be used during the optical black pixels, either together
with CLPOB or separately. The CLPDM pulse should be a
minimum of 4 pixels wide.
PxGA
The
PxGA
provides separate gain adjustment for the individual color
pixels. A programmable gain amplifier with four separate values,
the
PxGA
has the capability to
“
multiplex
”
its gain value on a
pixel-to-pixel basis (see Figure 37). This allows lower output
color
pixels to be gained up to match higher output color pixels.
Also, the
PxGA
may be used to adjust the colors for white balance,
reducing
the amount of digital processing that is needed. The four
different
gain values are switched according to the
“
color
steering
”
circuitry. Seven different color steering modes for dif-
ferent types of CCD color filter arrays are programmed in the
AD9891/AD9895 AFE CTLMODE Register, at Addr 0x06
(see Figures 39a
–
39g for internal color steering timing). For
0dB TO 36dB
CLPDM
CCDIN
DIGITAL
FILTER
CLPOB
DC RESTORE
OPTICAL BLACK
CLAMP
0.1 F
ADC
VGA
8-BIT
DAC
CLAMP LEVEL
REGISTER
8
VGA GAIN
REGISTER
10
CDS
INTERNAL
V
REF
2V FULL
SCALE
–2dB TO +10dB
10
or
12
PRECISION
TIMING
GENERATION
0.1 F
0.1 F
BYP1
BYP2
SHPSHD
PxGA
1.5V
OUTPUT
DATA
LATCH
1.0 F
REFT
1.0 F
REFB
DOUT
PHASE
V-H
TIMING
GENERATION
SHP
SHD
DOUT
PHASE
CLPDM CLPOB PBLK
PBLK
1.0V
2.0V
DOUT
0.1 F
BYP3
INPUT OFFSET
CLAMP
Figure 36. AFE Block Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9895KBC | CCD Signal Processors with Precision Timing⑩ Generator |
| AD9911BCPZ | 500 MSPS Direct Digital Synthesizer with 10-Bit DAC |
| AD9911BCPZ-REEL7 | 500 MSPS Direct Digital Synthesizer with 10-Bit DAC |
| AD9948KCPZ | 10-Bit CCD Signal Processor with Precision Timing⑩ Core |
| AD9948KCPZRL | 10-Bit CCD Signal Processor with Precision Timing⑩ Core |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ad9891kbcz | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9895 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processors with Precision Timing⑩ Generator |
| AD9895KBC | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3V/5V 64-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:12 BIT 30 MHZ AFE & PRGM TIMING GENERATO - Bulk |
| AD9895KBCRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3V/5V 64-Pin CSP-BGA T/R |
| AD9895KBCZ | 功能描述:IC CCD SIGNAL PROC/GEN 64-CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。