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| 型號： | AD9865BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Broadband Modem Mixed-Signal Front End |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QCC64 |
| 封裝： | MO-220-VMMD, LFCSP-64 |
| 文件頁數(shù)： | 41/48頁 |
| 文件大?。?/td> | 1672K |
| 代理商： | AD9865BCP |
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AD9865
Because the CPGA processes signals in the continuous time
domain, its performance vs. bias setting remains mostly
independent of the sample rate. Table 25 shows how the typical
current consumption seen at AVDD (Pins 35 and 40) varies as a
function of Bits (7:5), while the remaining bits are maintained at
their default settings of 0. Only four of the possible settings
result in any reduction in current consumption relative to the
default setting. Reducing the bias level typically results in a
degradation in the THD vs. frequency performance as shown in
Figure 80. This is due to a reduction of the amplifier’s unity gain
bandwidth, while the SNR performance remains relatively
unaffected.
Rev. A | Page 41 of 48
Table 25. Analog Supply Current vs. CPGA Bias Settings at
f
ADC
= 65 MSPS
Bit 7
Bit 6
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Bit 5
0
1
0
1
0
1
0
1
mA
0
27
42
51
55
27
69
27
0
CPGA BIAS SETTING-BITS (7:5)
S
T
000
100
010
011
001
65.0
40.0
–20
–70
–65
–60
–55
–50
–45
–40
–35
–30
–25
42.5
45.0
47.5
50.0
52.5
55.0
57.5
60.0
62.5
SNR_RxPGA = 0dB
SNR_RxPGA = 36dB
THD_RxPGA = 0dB
THD_RxPGA = 36dB
Figure 80. THD vs. f
IN
Performance and RxPGA Bias Settings
(000,001,010,100 with RxPGA = 0 and +36 dB and AIN = 1 dBFS,
LPF set to 26 MHz, and f
ADC
= 50 MSPS)
The SPGA is implemented as a switched capacitor amplifier;
therefore, its performance vs. bias level is mostly dependent on
the sample rate. Figure 81 shows how the typical current
consumption seen at AVDD (Pin 35 and Pin 40) varies as a
function of Bits (4:3) and sample rate, while the remaining bits
are maintained at the default setting of 0. Figure 82 shows how
the SNR and THD performance is affected for a 10 MHz sine
wave input as the ADC sample rate is swept from 20 MHz to 80
MHz. The SNR and THD performance remains relatively stable,
suggesting that the SPGA bias can often be reduced from its de-
fault setting without impacting the device’s overall performance.
0
ADC SAMPLE RATE (MSPS)
I
A
20
30
40
50
60
70
80
210
170
175
180
185
190
195
200
205
01
00
10
11
Figure 81. AVDD Current vs. SPGA Bias Setting and Sample Rate
0
SAMPLE RATE (MSPS)
S
T
20
80
60
70
30
40
50
61
51
–54
–74
–72
–70
–68
–66
–64
–62
–60
–58
–56
52
53
54
55
56
57
58
59
60
SNR-00
SNR-01
SNR-10
SNR-11
THD-00
THD-01
THD-10
THD-11
Figure 82. SNR and THD Performance vs. f
ADC
and SPGA Bias Setting with
RxPGA = 0 dB, f
IN
= 10 MHz, LPF set to 26 MHz, and AIN = 1 dBFS
The ADC is based on a pipeline architecture with each stage
consisting of a switched capacitor amplifier. Therefore, its per-
formance vs. bias level is mostly dependent on the sample rate.
Figure 83 shows how the typical current consumption seen at
AVDD (Pins 35 and 40) varies as a function of Bits (2:0) and
sample rate, while the remaining bits are maintained at the
default setting of 0. Setting Bit 4 or Register 0x07 corresponds
to the 011 setting, and the settings of 101 and 111 result in
higher current consumption. Figure 84 shows how the SNR and
THD performance are affected for a 10 MHz sine wave input
for the lower power settings as the ADC sample rate is swept
from 20 MHz to 80 MHz.
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| AD9865BCPRL | 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP T/R |
| AD9865BCPZ | 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9865BCPZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9865BCPZRL | 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點:- 封裝/外殼:48-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤 |
| AD9865BCPZRL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
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