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參數(shù)資料
| 型號： | AD9858/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9858 |
| 產(chǎn)品培訓模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計資源： | Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109) |
| 標準包裝： | 1 |
| 主要目的： | 計時，直接數(shù)字合成（DDS） |
| 已用 IC / 零件： | AD9858/TL |
| 已供物品： | 板 |
| 其它名稱： | AD9858/PCB AD9858/PCB-ND |
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AD9858
Rev. C | Page 5 of 32
Parameter
Temp
Test Level
Min
Typ
Max
Unit
TIMING CHARACTERISTICS
Serial Control Bus
Maximum Frequency
Full
IV
10
MHz
Minimum Clock Pulse Width Low (tPWL)
Full
IV
5.5
ns
Minimum Clock Pulse Width High (tPWH)
Full
IV
15
ns
Maximum Clock Rise/Fall Time
Full
IV
1
ns
Minimum Data Setup Time (tDS)
Full
IV
7
ns
Minimum Data Hold Time (tDH)
Full
IV
0
ns
Maximum Data Valid Time (tDV)
Full
IV
20
ns
Parallel Control Bus10
WR Minimum Low Time (tWRLOW)
Full
IV
3
ns
WR Minimum High Time (tWRHIGH)
Full
IV
6
ns
WR Minimum Period (tWR)
Full
IV
9
ns
Address to WR Setup (tASU)
Full
IV
3
ns
Address to WR Hold (tAHU)
Full
IV
0
ns
Data to WR Setup (tDSU)
Full
IV
3.5
ns
Data to WR Hold (tDHU)
Full
IV
0
ns
Miscellaneous Timing Specifications
REFCLK to SYNCLK
Full
V
2.5
ns
FUD/PS[1:0] to SYNCLK Setup Time11
Full
IV
4
ns
FUD/PS[1:0] to SYNCLK Hold Time11
Full
IV
0
ns
REFCLK to SYNCLK Delay
Full
IV
2.5
3
ns
DATA LATENCY (PIPELINE DELAY)
FTW/POW to DAC Output
25°C
IV
83
SYSCLK
cycles12
DFTW to DAC Output
25°C
IV
99
SYSCLK
cycles12
1 REFCLK input is internally dc biased. AC coupling should be used.
2 Reference clock frequency is selected to ensure that the second harmonic is out of the bandwidth of interest.
3 PD inputs set at 400 MHz with divide-by-4 enabled.
4 The charge pump current is programmable in eight discrete steps; minimum value assumes current sharing.
5 For 0.75 V < VCP < CPVDD 0.75 V.
6 These differential inputs are internally dc biased. AC coupling should be used.
7 The charge pump supply voltage can range from 4.75 V to 5.25 V.
8 DAC output is differential open collector.
9 For 1 dB output compression; input power measured at 50 Ω.
10 See Figure 35 and Figure 36 for timing diagrams.
11 See Figure 34 for timing diagram.
12 SYSCLK = REFCLK/x, where x is 1 or 2, as set using CFR[6].
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9858TLPCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer |
| AD9858XSV | 制造商:Analog Devices 功能描述: |
| AD9859 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9859/PCB | 制造商:Analog Devices 功能描述:NCO, 400MSPS 10 BIT, 1.8V CMOS DIRECT DGTL SYNTHESIZER - Bulk |
| AD9859/PCBZ | 功能描述:BOARD EVAL FOR AD9859 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:AgileRF™ 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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