參數(shù)資料
型號(hào): AD9858/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 15/32頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9858
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),直接數(shù)字合成(DDS)
已用 IC / 零件: AD9858/TL
已供物品:
其它名稱: AD9858/PCB
AD9858/PCB-ND
AD9858
Rev. C | Page 22 of 32
REGISTER MAP
The registers are listed in Table 6. The serial address and parallel address numbers associated with each of the registers are shown in
hexadecimal format. Square brackets [] are used to reference specific bits or ranges of bits. For example, [3] designates Bit 3, and [7:3]
designates the range of bits from 7 down to 3, inclusive.
Table 6.
Register
Address
(MSB)
(LSB)
Default
Name
Ser
Par
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value
Profile
Control
function
register
(CFR)
0x00
[7:0]
Not
used
2 GHz
divider
disable
SYNCLK
disable
Mixer
power-
down
Phase
detect
power-
down
Power-
down
SDIO
input
only
LSB first
0x18
N/A
0x01
[15:8]
Freq.
sweep
enable
Enable
sine
output
Charge
pump
offset
Phase detector
divider ratio (N)
(see Table 10)
Charge
pump
polarity
Phase detector
divider ratio (M)
(see Table 11)
0x00
N/A
0x02
[23:16]
Auto Clr
freq.
accum
Auto Clr
phase
accum
Load
delta
freq
timer
Clear
freq
accum
Clear
phase
accum
Not
used
Fast
lock
enable
FTW for
fast lock
0x00
N/A
0x03
[31:24]
Frequency detect
mode charge
pump current
(see Table 7)
Final closed-loop
mode charge pump current
(see Table 8)
Wide closed-loop mode
charge pump current
(see Table 9)
0x00
N/A
Delta freq.
tuning
word
(DFTW)
0x01
0x04
Delta Frequency Word[7:0]
N/A
0x05
Delta Frequency Word[15:8]
N/A
0x06
Delta Frequency Word[23:16]
N/A
0x07
Delta Frequency Word[31:24]
N/A
Delta
frequency
ramp rate
(DFRRW)
0x02
0x08
Delta Frequency Ramp Rate Word[7:0]
N/A
0x09
Delta Frequency Ramp Rate Word[15:8]
N/A
Frequency
Tuning
Word 0
(FTW0)
0x03
0x0A
Frequency Tuning Word 0[7:0]
0x00
0
0x0B
Frequency Tuning Word 0[15:8]
0x00
0
0x0C
Frequency Tuning Word 0[23:16]
0x00
0
0x0D
Frequency Tuning Word 0[31:24]
0x00
0
Phase
Offset
Word 0
(POW0)
0x04
0x0E
Phase Offset Word 0[7:0]
0x00
0
0x0F
Not used
Phase Offset Word 0[13:8]
0x00
0
Frequency
Tuning
Word 1
(FTW1)
0x05
0x10
Frequency Tuning Word 1[7:0]
1
0x11
Frequency Tuning Word 1[15:8]
1
0x12
Frequency Tuning Word 1[23:16]
1
0x13
Frequency Tuning Word 1[31:24]
1
Phase
Offset
Word 1
(POW1)
0x06
0x14
Phase Offset Word 1[7:0]
1
0x15
Not used
Phase Offset Word 1[13:8]
1
Frequency
Tuning
Word 2
(FTW2)
0x07
0x16
Frequency Tuning Word 2[7:0]
2
0x17
Frequency Tuning Word 2[15:8]
2
0x18
Frequency Tuning Word 2[23:16]
2
0x19
Frequency Tuning Word 2[31:24]
2
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