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參數(shù)資料
| 型號： | AD9858/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9858 |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計資源： | Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，直接數(shù)字合成（DDS） |
| 已用 IC / 零件： | AD9858/TL |
| 已供物品： | 板 |
| 其它名稱： | AD9858/PCB AD9858/PCB-ND |
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AD9858
Rev. C | Page 19 of 32
SYNCLK
SYSCLK
FUD REGISTERED
FUD EDGE DETECTED
FUD REGISTERED
FUD EDGE DETECTED
VALUE 2
VALUE 1
I/O BUFFER
MEMORY
CONTROL
REGISTER
DATA
VALUE 0
VALUE 1
VALUE 2
(ASYNCHRONOUSLY LOADED VIA I/O PORT)
FUD
*
(ASYNCHRONOUSLY LOADED VIA I/O PORT)
*FUD IS AN INPUT PROVIDED BY THE USER THAT MUST BE SET UP AND HELD AROUND RISING EDGES OF SYNCLK. THE OCCURRENCE OF THE
RISING EDGE OF SYNCLK DURING THE HIGH STATE OF THE UPDATE REGS SIGNAL CAUSES THE BUFFER MEMORY CONTENTS TO BE
TRANSFERRED INTO THE CONTROL REGISTERS. SIMILARLY, A STATE CHANGE ON THE PS0 OR PS1 PIN IS EQUIVALENT TO ASSERTING A VALID
FUD SEQUENCE. NOTE: I/O UPDATES ARE SYNCHRONOUS TO THE SYNCLK SIGNAL, REGARDLESS OF THE SYNCHRONIZATION MODE SELECTED.
03
16
6-
0
37
Figure 34. I/O Synchronization Timing Diagram
Frequency Planning
To achieve the best possible spurious performance when using
the AD9858 in a hybrid synthesizer configuration, employ
frequency planning. Frequency planning consists of being
aware of the mechanisms that determine the location of the
worst-case spurs and then using the appropriate loop tuning
parameters to place these spurs either outside the loop bandwidth,
so that they are attenuated, or completely outside the frequency
range of interest.
When using the fractional divider configuration, the worst-case
spurs occur whenever the images of the DAC harmonics fold
back such that they are close to the DAC fundamental or carrier
frequency. If these images fall within the loop bandwidth, they
are gained up by approximately 20 × logN, where N is the gain
in the loop. If N is relatively high, these spurs can still realize
significant gain, even if they are slightly outside the loop band-
width, because the loop attenuation rate is typically 20 dB/dec
in this region. DAC images occur at
N × fCLOCK ± M × fOUT
where N and M are integer multiples of fCLOCK and fOUT,
respectively.
Figure 20 shows a high spurious condition where the low-order
odd harmonics are folding back around the fundamental. Figure 24
shows that the worst spurs are confined to a narrow region
around the carrier and that wideband spurs are attenuated.
Figure 17 shows an alternate frequency plan that results in the
same carrier frequency. The output frequency of the DAC is set by
fOUT = fCLOCK × FTW/2N
This makes it possible to produce the same fOUT by different
combinations of fCLOCK and FTW. In this case, the worst DAC
spurs are placed well outside the loop bandwidth such that they
are attenuated below the noise floor. Figure 21 shows a wideband
plot for this frequency plan.
Other frequency combinations that result in high spurious signals
are when subharmonics of fCLOCK fall within or near the loop
bandwidth. To avoid this, ensure that the DAC fOUT is sufficiently
offset from the subharmonics of fCLOCK such that these products
are attenuated by the loop.
Frequency planning for the translation loop is similar in that
the DAC images and the fCLOCK subharmonics need to be
spurious configuration where odd order images are folding
alternative frequency plan that generates the same carrier
frequency with low spurious content. Because this loop also
requires a mixer LO frequency, additional care is required in
planning for this frequency arrangement. Generally, there is
some mixer LO feedthrough. The amount of feedthrough
depends on the PCB layout isolation as well as the mixer LO
power level, but levels of 80 dBc can typically be achieved.
Figure 26 shows results for a situation where the mixer LO
component shows up in the spectrum at 1.41 GHz, and another
spur component shows up at Mixer LO + fCLOCK/8. This places
the mixer LO frequency well outside the bandwidth of interest,
resulting in the spectrum shown in Figure 25.
PROGRAMMING THE AD9858
The transfer of data from the user to the DDS core of the device
is a 2-step process. In a write operation, the user first writes the
data to the I/O buffer by using either the parallel port (which
includes bits for address and data) or the serial port (where the
address and data are combined in a serial word). Regardless of
the method used to enter data to the I/O buffer, the DDS core
cannot access the data until the data is latched into the memory
registers from the I/O buffer. Toggling the FUD pin or changing
one of the profile select pins causes an update of all elements of
the I/O buffer memory into the register memory of the DDS core.
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相關(guān)代理商/技術(shù)參數(shù) |
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