參數(shù)資料
型號: AD9856
廠商: ANALOG DEVICES INC
元件分類: 衰減器
英文描述: CMOS 180 MHz Quadrature Digital Upconverter(時鐘頻率為180MHz,CMOS的積分上變頻器)
中文描述: RF/MICROWAVE UP CONVERTER
文件頁數(shù): 17/19頁
文件大?。?/td> 244K
代理商: AD9856
AD9856 Preliminary Technical Information
17
This Advanced Datasheet describes a product which is in the development stage. Specifications and pin-out are subject to change without notice. For additional information please contact Analog Devices,
High-speed Converter Group, 7910 Triad Center Drive, Greensboro, NC, 27409 Tel: 336/605-4365
REV. 6/2/98
Understanding and Using Pin Selectable Modulator Profiles
The AD9856 Quadrature Digital Upconverter is capable of storing four pre-configured modulation modes
called “profiles” that define the following:
Output frequency - 32-bits (register names: FTW1, FTW2, FTW3, FTW4)
Interpolation rate - 6 bits (bit names: INT1, INT2, INT3, INT4)
Spectral inversion status - 1 bit (bit names: SI1, SI2, SI3, SI4)
Bypass 3
rd
half-band filter - 1 bit
(bit names: BPHB1, BPHB2, BPHB3, BPHB4)
Gain control of AD8320 - 8 bits (register names: GS1, GS2, GS3, GS4)
Output Frequency:
This attribute consists of four 8-bit words loaded into four register addresses to form a
32-bit frequency tuning word (FTW) for each profile. The lowest register address corresponds to the least
significant 8-bit word . Ascending addresses correspond to increasingly significant 8-bit words. The output
frequency equation is given as: Fout = (FTW*Fclk)/2^32.
Interpolation Rate:
Consists of a 6-bit word representing the allowed interpolation values from 1 to 63.
Interpolation is the mechanism used to “up-sample” or multiply the input data rate such that it exactly matches
that of the DDS sample rate (Fmax). This implies that the system clock must be an exact multiple of the
symbol rate. This 6-bit word represents the 6 MSB’s of the eight bits allocated for that address. The remaining
two bits contain the spectral inversion status bit and half-band bypass bit (see below).
Spectral Inversion:
Consists of a 1-bit word that when at logic 0 the default or “non-inverted” output from
the adder is sent to the following stages. A logic 1 will cause the inverted output to be sent to the following
stages. The non-inverted output is described as I*Cos(wt) - Q*Sin(wt). The inverted output is described as
I*Cos(wt) + Q*Sin(wt). This bit is located adjacent to the LSB at the same address as the interpolation rate
(see above).
By-pass Third Half-Band Filter:
A 1- bit word located in the LSB position of the same address as the
interpolation rate (see above). When this bit is logic 0, the third half-band filter (one of three such filters) is
engaged and its inherent 2X interpolation rate is applied. When this bit is logic 1, the third half-band filter is
by-passed and the 2X interpolation rate is negated. This allows users to input higher data rates - rates that
may be too high for the minimum interpolation rate if all three half-band filters with their inherent 2X
interpolation rate are engaged. The overall effect is to reduce minimum interpolation rate from X8 to X4.
AD8320 Gain Control:
An 8-bit word that controls the gain of an AD8320 Programmable Gain Amplifier
connected to the AD9853 with the 3-bit SPI interface bus. Gain range is from -10 dB (00hex) to +26 dB
(FFhex). The gain is linear in V/V/LSB and follows the equation: Av = .316 + .077 x Code. Where “Code”
is the decimal equivalent of the 8-bit gain word.
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