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參數(shù)資料
| 型號： | AD9856 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 衰減器 |
| 英文描述： | CMOS 180 MHz Quadrature Digital Upconverter(時鐘頻率為180MHz,CMOS的積分上變頻器) |
| 中文描述： | RF/MICROWAVE UP CONVERTER |
| 文件頁數(shù)： | 14/19頁 |
| 文件大?。?/td> | 244K |
| 代理商： | AD9856 |
AD9856 Preliminary Technical Information
14
This Advanced Datasheet describes a product which is in the development stage. Specifications and pin-out are subject to change without notice. For additional information please contact Analog Devices,
High-speed Converter Group, 7910 Triad Center Drive, Greensboro, NC, 27409 Tel: 336/605-4365
REV. 6/2/98
Input Formatter - Clock Domains
The AD9856 contains programmable phase-locked loop circuitry that multiplies up the external reference clock
frequency input (REFCLK) by integer values, programmable from 4 to 20, to generate the internal reference clock
frequency (Fmax). The maximum internal clock frequency is 180 MHz. All other internal clock domains are generated
from Fmax. Separate clock domains exist for the Halfband filters and input format logic.
Equations 1-5 relate the clock domains to REFCLK for profiles that do not bypass the third Halfband filter. MULT is
the programmable 5-bit register value. INTERPRATE is the current interpolation rate of the CIC filter as selected by
the profile bits.
Fmax = REFCLK*MULT=F5
F4 = (REFCLK*MULT)/INTERPRATE
F3 = F4/2 = (REFCLK*MULT)/(INTERPRATE*2)
F2 = F3/2= (REFCLK*MULT)/(INTERPRATE*4)
F1 = F2/2=(REFCLK*MULT)/(INTERPRATE*8)
(EQ. 1)
(EQ. 2)
(EQ. 3)
(EQ. 4)
(EQ. 5)
The input data format data rate is a function of the Fmax clock rate and the input format mode chosen via the
REG1<1:0> bits. If the REG1<1:0> bit is programmed to “1X”, the input format selected is a 12-bit word (full word
mode). For burst operation, in full word mode, the input timing diagram is shown in figure 9. The data rate, related to
Fmax, is given in equation 6.
Fin = F2 = (REFCLK*MULT)/(INTERPRATE*4)
(EQ. 6)
If the REG1<1:0> bits are programmed to 01, the input format selected is a 6-bit word (half word mode). For burst
mode operation in half word mode, the input timing diagram is shown below in figure 10. The data rate, related to
Fmax is given by equation 7.
Fin = F3 = (REFCLK*MULT)/(INTERPRATE*2)
(EQ. 7)
If the REG1<1:0> bits are programmed to 00, the input format selected is a 3-bit word (quarter mode). For burst mode
operation in quarter word mode, the input timing diagram is shown below in figure 11. The data rate, related to Fmax,
is given by equation 8.
Fin = F4 = (REFCLK*MULT)/INTERPRATE
(EQ. 8)
I/Q Data Synchronization
The AD9856 accepts I/Q data pairs in 2’s complement numbering system, in three different word length modes. For all
input format modes, the AD9856 input formatter logic outputs to the data path circuitry, parallel 12-bit I/Q pairs at the
data rate F1, as given in equation 5 above. If the BPHB3 filter is set, the parallel 12-bit I/Q pairs are output at F2 as
described in equation 4.
Programmable input format modes are: 12-bit, 6-bit, or 3-bit, in Burst Mode operation. In Continuous Mode
operation, only the 12-bit input format is accepted.
相關(guān)PDF資料 |
PDF描述 |
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| AD9857 | CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter |
| AD9857AST | CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter |
| AD9865 | Broadband Modem Mixed-Signal Front End |
| AD9865-EB | Broadband Modem Mixed-Signal Front End |
| AD9865BCP | Broadband Modem Mixed-Signal Front End |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9856/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For Digital Up Converter 56 Pin LFCSP Ep 制造商:Analog Devices 功能描述:DGTL UP CNVRTR 56LFCSP - Bulk |
| AD9856AST | 制造商:Analog Devices 功能描述:Digital Up Converter 48-Pin LQFP Tray 制造商:Analog Devices 功能描述:IC MODULATOR DIGITAL |
| AD9856ASTZ | 功能描述:IC UPCONVERTER DGTL QUAD 48TQFP RoHS:是 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:AD9856 標(biāo)準(zhǔn)包裝:100 系列:* |
| AD9857 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter |
| AD9857/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For AD9857 |
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