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參數(shù)資料
| 型號(hào)： | AD9856 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | 衰減器 |
| 英文描述： | CMOS 180 MHz Quadrature Digital Upconverter(時(shí)鐘頻率為180MHz,CMOS的積分上變頻器) |
| 中文描述： | RF/MICROWAVE UP CONVERTER |
| 文件頁(yè)數(shù)： | 15/19頁(yè) |
| 文件大?。?/td> | 244K |
| 代理商： | AD9856 |
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AD9856 Preliminary Technical Information
15
This Advanced Datasheet describes a product which is in the development stage. Specifications and pin-out are subject to change without notice. For additional information please contact Analog Devices,
High-speed Converter Group, 7910 Triad Center Drive, Greensboro, NC, 27409 Tel: 336/605-4365
REV. 6/2/98
12-bit Input Format
Figures 9-11 show the timing relationship between TxEnable and D<11:0> inputs. Note that the AD9856 expects the
12-bit I data followed by the 12-bit Q data. I and Q are 2’s complement numbers, the sign bit is D<11> in notation
I<11:0>, Q<11:0>.
Figure 9. 12-bit I/Q Input Word Format Diagram
TxEnable
12-bit Input Word
I0
Q0
I1
Q1
I2
Q2
IN
QN
Figure 10. 6-bit I/O Input Word Format Diagram
TxEnable
6-bit Input Word Note: IN0 (11:6) and IN1 (5:0) are combined in I<11:0> (same for Q)
I00
I01
Q00
Q01
I10
I11
IN0
IN1
Figure 11. 3-bit I/O Input Word Format Diagram
TxEnable
3-bit Input Word Note: IN0, IN1, and IN2 are combined I<11:0> (same for Q)
I00
I01
I02
Q00
Q01
Q02
QN0
QN1
The AD9856 actually uses the Fmax clock rate to sample the D<11:0> inputs. The user only has to provide data, at
the proper data rate, synchronous to the rising edge of TxEnable. The data rate change from Fmax to F1 occurs
approximately in the middle of each I/Q input period. (See timing diagram in figure 12 below).
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| AD9856/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For Digital Up Converter 56 Pin LFCSP Ep 制造商:Analog Devices 功能描述:DGTL UP CNVRTR 56LFCSP - Bulk |
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| AD9857 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter |
| AD9857/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For AD9857 |
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