參數(shù)資料
型號(hào)： AD9778A-DPG2-EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 23/56頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD9778A
標(biāo)準(zhǔn)包裝： 1
系列： *
DAC 的數(shù)量： 2
位數(shù)： 14
采樣率（每秒）： 1G
數(shù)據(jù)接口： 并聯(lián)
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： *
已用 IC / 零件： AD9778A
AD9776A/AD9778A/AD9779A
Rev. B | Page 3 of 56
REVISION HISTORY
9/08—Rev. A to Rev. B
Changed Serial Peripheral Interface (SPI) to 3-Wire Interface
Throughout ...................................................................................1
Change to Features Section..............................................................1
Change to Applications Section ......................................................1
Changes to Integral Nonlinearity (INL) Parameter, Table 1 .......5
Changes to DAC Clock Input (REFCLK+, REFCLK)
Parameter, Table 2 ........................................................................6
Changes to Input Data Parameter, Table 3.....................................7
Changes to Hold Time Parameters, Table 3...................................7
Added 3-Wire Interface Parameter, Table 3...................................7
Added Reset Parameter, Table 3 ......................................................7
Changes to Endnotes, Table 3..........................................................7
Added Exposed Pad Notation to Figure 3, Changes to Table 7 ......10
Added Exposed Pad Notation to Figure 4, Changes to Table 8 ......12
Added Exposed Pad Notation to Figure 5, Changes to Table 9 ......14
Changes to DATACLK Delay Range Section ..............................25
Changes to Version Register Section ............................................25
Changes to Table 10 ........................................................................25
Changes to Table 12 ........................................................................26
Changes to Table 13 ........................................................................28
Changes to Table 14 ........................................................................29
Changes to Interpolation Filter Architecture Section ................33
Changes to Figure 60 ......................................................................34
Changes to Table 19 ........................................................................36
Changes to Interpolation Filter Bandwidth Limits Section.......37
Changes to Figure 70 ......................................................................37
Added Digital Modulation Section...............................................37
Added Table 20 and Table 21; Renumbered Sequentially..........38
Added Inverse Sinc Filter Section .................................................38
Added Figure 71; Renumbered Sequentially ...............................38
Changes to Clock Multiplication Section ....................................39
Changes to Figure 72 ......................................................................39
Changes to Configuring the PLL Band Select Value Section ....39
Changes to Configuring the PLL Band Select with Temperature
Sensing Section...........................................................................41
Changes to Known Temperature Calibration with Memory
Section .........................................................................................41
Changes to Set-and-Forget Device Option Section....................41
Added Table 26 ................................................................................41
Changes to Internal Reference Section.........................................43
Changed Transmit Path Gain and Offset Correction Heading to
Gain and Offset Correction ......................................................44
Changes to I/Q Channel Gain Matching Section .......................44
Changes to Auxiliary DAC Operation Section ...........................44
Replaced Figure 79..........................................................................45
Deleted Figure 79; Renumbered Sequentially .............................41
Changes to LO Feedthrough Compensation Section.................45
Changes to Table 28 ........................................................................47
Changes to Optimizing the Data Input Timing Section............48
Change to Synchronization Logic Overview Section.................49
Changes to Figure 88 ......................................................................49
Changes to Figure 101 ....................................................................53
Deleted Using the ADL5372 Quadrature Modulator Section and
Figure 104....................................................................................51
Deleted Evaluation Board Schematics Section and Figure 105;
Renumbered Sequentially .........................................................52
Deleted Figure 106 ..........................................................................53
Deleted Figure 107 ..........................................................................54
Deleted Figure 108 ..........................................................................55
Deleted Figure 109 ..........................................................................56
Deleted Figure 110 ..........................................................................57
Deleted Figure 111 ..........................................................................58
Deleted Figure 112 ..........................................................................59
Updated Outline Dimensions........................................................60
3/08—Rev. 0 to Rev. A
Changes to Features ..........................................................................1
Added Note 2 .....................................................................................4
Changes to Table 2 ............................................................................5
Changes to Table 3 ............................................................................6
Changes to Thermal Resistance Section ........................................7
Inserted Table 6 .................................................................................8
Changes to Pin 39 Description, Table 7 .........................................9
Changes to Pin 39 Description, Table 8 .......................................10
Changes to Pin 39 Description, Table 9 .......................................12
Changes to Theory of Operation Section ....................................23
Changes to Table 10 ........................................................................23
Changes to Table 13 ........................................................................26
Changes to Table 14 ........................................................................27
Changes to Interpolation Filter Architecture Section ................33
Replaced Sourcing the DAC Sample Clock Section ...................36
Replaced Transmit Path Gain and Offset Correction Section ........40
Replaced Input Data Ports Section ...............................................42
Replaced Device Synchronization Section ..................................45
Deleted Figure 112 to Figure 117 ..................................................58
8/07—Revision 0: Initial Version
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