參數(shù)資料
型號： AD9778A-DPG2-EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 22/56頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD9778A
標(biāo)準(zhǔn)包裝： 1
系列： *
DAC 的數(shù)量： 2
位數(shù)： 14
采樣率（每秒）： 1G
數(shù)據(jù)接口： 并聯(lián)
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： *
已用 IC / 零件： AD9778A
AD9776A/AD9778A/AD9779A
Rev. B | Page 29 of 56
Table 14. 3-Wire Interface Register Description
Register
Address
Bits
Register Name
Parameter
Function
Default
Comm
0x00
7
SDIO bidirectional
0: use SDIO pin as input data only.
1: use SDIO as both input and output data.
0
0x00
6
LSB/MSB first
0: first bit of serial data is MSB of data byte.
1: first bit of serial data is LSB of data byte.
0
0x00
5
Software reset
Bit must be written with a 1 and then 0 to soft reset
the 3-wire interface register map.
0
0x00
4
Power-down mode
0: all circuitry is active.
1: disable all digital and analog circuitry, only
3-wire interface port is active.
0x00
3
Auto power-down enable
Controls auto power-down mode. See the Power-
0
0x00
1
PLL lock indicator
(read only)
0: PLL is not locked.
1: PLL is locked.
Digital Control
0x01
7:6
Interpolation Factor[1:0]
00: 1× interpolation.
01: 2× interpolation.
10: 4× interpolation.
11: 8× interpolation.
00
0x01
5:2
Filter Modulation Mode[3:0]
See Table 19 for filter modes.
0000
0x01
1
DATACLK Delay[4]
Sets MSB of delay of REFCLK input to DATACLK
output.
0
0x01
0
Zero stuffing enable
0: zero stuffing off.
1: zero stuffing on.
0
0x02
7
Data format
0: twos compliment.
1: unsigned binary.
0
0x02
6
Single port
0: both P1D and P2D data ports enabled.
1: data for both DACs received on P1D data port.
0
0x02
5
Real mode
0: enable Q path for signal processing.
1: disable Q path data (internal Q channel clocks
disabled, I and Q modulators disabled).
0
0x02
4
DATACLK delay enable
Enables the DATACLK delay feature. More details
on this feature are shown in the Optimizing the
0x02
3
Inverse sinc enable
0: inverse sinc filter disabled.
1: inverse sinc filter enabled.
0
0x02
2
DATACLK invert
0: output DATACLK same phase as internal data
sampling clock, DCLK_SMP signal.
1: output DATACLK opposite phase as internal data
sampling clock, DCLK_SMP signal.
0
0x02
1
TxEnable invert
Inverts the polarity of Pin 39, the TXENABLE input
pin (also functions as IQSELECT).
0
0x02
0
Q first
0: in interleaved mode, the I data precedes the
Q data on the input port.
1: in interleaved mode, the Q data precedes the
I data on the input port.
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參數(shù)描述
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