參數(shù)資料
型號(hào)： AD9777
廠商： Analog Devices, Inc.
英文描述： 16-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter
中文描述： 16位，160 MSPS的2X/4X/8X TxDAC系列插雙D / A轉(zhuǎn)換
文件頁數(shù)： 21/48頁
文件大?。?/td> 6021K
代理商： AD9777
REV. 0
AD9777
–21–
CHARGE
PUMP
PHASE
DETECTOR
CLK+
CLOCK
DISTRIBUTION
CIRCUITRY
VCO
AD9777
CLK–
SPI PORT
INTERNAL SPI
CONTROL
REGISTERS
PLL_LOCK
1 = LOCK
0 = NO LOCK
PLLVDD
LPF
INTERPOLATION
FILTERS,
MODULATORS,
AND DACS
2
8
INTERPOLATION
RATE
CONTROL
PLL DIVIDER
(PRESCALER)
CONTROL
PLL
CONTROL
(PLL ON)
1
INPUT
DATA
LATCHES
MODULATION
RATE
CONTROL
PRESCALER
4
Figure 12. PLL and Clock Circuitry with PLL Enabled
CHARGE
PUMP
PHASE
DETECTOR
CLK+
CLOCK
DISTRIBUTION
CIRCUITRY
VCO
AD9777
CLK–
SPI PORT
INTERNAL SPI
CONTROL
REGISTERS
PLL_LOCK
1 = LOCK
0 = NO LOCK
INTERPOLATION
FILTERS,
MODULATORS,
AND DACS
2
8
INTERPOLATION
RATE
CONTROL
PLL DIVIDER
(PRESCALER)
CONTROL
PLL
CONTROL
(PLL ON)
1
INPUT
DATA
LATCHES
MODULATION
RATE
CONTROL
PRESCALER
4
Figure 13. PLL and Clock Circuitry with PLL Disabled
In addition, if the zero stuffing option is enabled, the VCO will
double its speed again. Phase noise may be slightly higher with
the PLL enabled. Figure 14 illustrates typical phase noise per-
formance of the AD9777 with 2
×
interpolation and various
input data rates. The signal synthesized for the phase noise
measurement was a single carrier at a frequency of f
DATA
/4.
The repetitive nature of this signal eliminated quantization noise
and distortion spurs as a factor in the measurement. Although
the curves blend together in Figure 14, the different conditions
are called out here for clarity.
f
DATA
PLL
Prescaler Ratio
125 MSPS
125 MSPS
100 MSPS
75 MSPS
50 MSPS
Disabled
Enabled
Enabled
Enabled
Enabled
div1
div2
div2
div4
FREQUENCY OFFSET – MHz
P
–80
0
0
–70
–60
–50
–40
–30
–20
–10
–90
–110
–100
1
2
3
4
5
Figure 14. Phase Noise Performance
It is important to note that the resistor/capacitor needed for the
PLL loop filter is internal on the AD9777. This will suffice unless
the input data rate is below 10 MHz, in which case an external
series RC is required between the LPF and PLLVDD Pins.
POWER DISSIPATION
The AD9777 has three voltage supplies: AVDD, DVDD, and
CLKVDD. Figures 15, 16, and 17 show the current required
from each of these supplies when each is set to the 3.3 V nomi-
nal specified for the AD9777. Power dissipation (P
D
) can easily
be extracted by multiplying the given curves by 3.3. As Figure 15
shows, I
DVDD
is very dependent on the input data rate, the
interpolation rate, and the activation of the internal digital
modulator. I
DVDD
, however, is relatively insensitive to the
modulation rate by itself. In Figure 16, I
AVDD
shows the same
type of sensitivity to data, interpolation rate, and the modulator
function but to a much lesser degree (<10%). In Figure 17,
I
CLKVDD
varies over a wide range yet is responsible for only a small
percentage of the overall AD9777 supply current requirements.
f
DATA
– MHz
0
50
I
D
0
100
150
200
50
100
150
200
250
300
350
400
8
(MOD. ON)
,
4
(MOD. ON)
,
2
(MOD. ON)
,
8
4
2
1
Figure 15. I
DVDD
vs. f
DATA
vs. Interpolation Rate,
PLL Disabled
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參數(shù)描述
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AD9777BSVZ 功能描述:IC DAC 16BIT DUAL 160MSPS 80TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND
AD9777BSVZ 制造商:Analog Devices 功能描述:IC 16-BIT DAC ((NW)) 制造商:Analog Devices 功能描述:IC, DAC, 16BIT, 400MSPS, TQFP-80
AD9777BSVZ 制造商:Analog Devices 功能描述:IC DAC 16BIT 400MSPS 80TQFP
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