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參數(shù)資料
| 型號： | AD9649BCPZRL7-40 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 40MSPS 32LFCSP |
| 標準包裝： | 1,500 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 40M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 65.8mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
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AD9649
Rev. 0 | Page 21 of
32
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive
to clock duty cycle. Commonly, a 50% duty cycle clock with ±5%
tolerance is required to maintain optimum dynamic performance,
as shown in Figure 52.
Jitter on the rising edge of the clock input can also impact dynamic
performance and should be minimized, as discussed in the Jitter
Considerations section of this datasheet.
80
75
70
65
60
55
50
40
45
10
20
30
40
50
60
70
80
POSITIVE DUTY CYCLE (%)
S
N
R
(
d
BF
S
)
0
85
39
-0
53
Figure 52. SNR vs. Clock Duty Cycle
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low fre-
quency SNR (SNRLF) at a given input frequency (fINPUT) due to
jitter (tJRMS) can be calculated by
SNRHF = 10 log[(2π × fINPUT × tJRMS)2 + 10
]
)
10
/
(
LF
SNR
In the previous equation, the rms aperture jitter represents the
clock input jitter specification. IF undersampling applications
are particularly sensitive to jitter, as illustrated in Figure 53.
80
75
70
65
60
55
50
45
1
10
100
1k
FREQUENCY (MHz)
S
NR
(
d
BF
S
)
0.5ps
0.2ps
0.05ps
1.0ps
1.5ps
2.0ps
2.5ps
3.0ps
0
853
9-
0
22
Figure 53. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases in
which aperture jitter may affect the dynamic range of the AD9649.
To avoid modulating the clock signal with digital noise, keep power
supplies for clock drivers separate from the ADC output driver
supplies. Low jitter, crystal-controlled oscillators make the best
clock sources. If the clock is generated from another type of source
(by gating, dividing, or another method), it should be retimed by
the original clock at the last step.
For more information, see the AN-501 Application Note and the
AN-756 Application Note, which are available on www.analog.com.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 54, the analog core power dissipated by the
AD9649 is proportional to its sample rate. The digital power dis-
sipation of the CMOS outputs are determined primarily by the
strength of the digital drivers and the load on each output bit.
The maximum DRVDD current (IDRVDD) can be calculated as
IDRVDD = VDRVDD × CLOAD × fCLK × N
where N is the number of output bits (15, in the case of the
AD9649).
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of fCLK/2. In practice, the DRVDD current is estab-
lished by the average number of output bits that are switching,
which is determined by the sample rate and the characteristics
of the analog input signal.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 54 was
taken using the same operating conditions as those used for the
Typical Performance Characteristics, with a 5 pF load on each
output driver.
85
75
65
55
80
70
60
50
45
35
40
10
20
30
40
50
60
70
80
CLOCK RATE (MSPS)
ANAL
O
G
C
O
RE
P
O
W
E
R
(
m
W
)
AD9649-80
AD9649-65
AD9649-40
AD9649-20
08
53
9-
05
1
Figure 54. Analog Core Power vs. Clock Rate
In SPI mode, the AD9649 can be placed in power-down mode
directly via the SPI port or by using the programmable external
MODE pin. In non-SPI mode, power-down is achieved by assert-
ing the PDWN pin high. In this state, the ADC typically dissipates
500 μW. During power-down, the output drivers are placed in a
high impedance state. Asserting the PDWN pin (or the MODE pin
in SPI mode) low returns the AD9649 to normal operating mode.
Note that PDWN is referenced to the digital output driver supply
(DRVDD) and should not exceed that supply voltage.
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