參數(shù)資料
型號(hào)： AD9649BCPZRL7-40
廠商： Analog Devices Inc
文件頁數(shù)： 13/32頁
文件大?。?/td> 0K
描述： IC ADC 14BIT 40MSPS 32LFCSP
標(biāo)準(zhǔn)包裝： 1,500
位數(shù)： 14
采樣率（每秒）： 40M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 65.8mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)單端，單極；1 個(gè)差分，單極
AD9649
Rev. 0 | Page 20 of
32
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9649 sample clock inputs,
CLK+ and CLK, with a differential signal. The signal is typi-
cally ac-coupled into the CLK+ and CLK pins via a transformer
or capacitors. These pins are biased internally (see Figure 46) and
require no external bias.
0.9V
AVDD
2pF
CLK–
CLK+
08
53
9-
0
16
Figure 46. Equivalent Clock Input Circuit
Clock Input Options
The AD9649 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of great concern, as described in the Jitter Considerations section.
Figure 47 and Figure 48 show two preferred methods for clock-
ing the AD9649. The CLK inputs support up to 4× the rated sample
rate when using the internal clock divider feature. A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF transformer or an RF balun.
0.1F
SCHOTTKY
DIODES:
HSMS2822
CLOCK
INPUT
50
100
CLK–
CLK+
ADC
Mini-Circuits
ADT1-1WT, 1:1 Z
XFMR
08
53
9-
01
7
Figure 47. Transformer-Coupled Differential Clock (3 MHz to 200 MHz)
0.1F
1nF
CLOCK
INPUT
1nF
50
CLK–
CLK+
SCHOTTKY
DIODES:
HSMS2822
ADC
08
53
9-
0
18
Figure 48. Balun-Coupled Differential Clock (Up to 4× Rated Sample Rate)
The RF balun configuration is recommended for clock frequen-
cies between 80 MHz and 320 MHz, and the RF transformer is
recommended for clock frequencies from 3 MHz to 200 MHz.
The back-to-back Schottky diodes across the transformer/balun
secondary limit clock excursions into the AD9649 to ~0.8 V p-p
differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9649 while
preserving the fast rise and fall times of the signal that are critical
to a low jitter performance.
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 49. The AD9510/AD9511/AD9512/
excellent jitter performance.
100
0.1F
240
240
50k
50k
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
ADC
AD951x
PECL DRIVER
0
853
9-
01
9
Figure 49. Differential PECL Sample Clock (Up to 4× Rated Sample Rate)
A third option is to ac couple a differential LVDS signal to the
sample clock input pins as shown in Figure 50. The AD9510/
clock drivers offer excellent jitter performance.
100
0.1F
50k
50k
CLK–
CLK+
ADC
CLOCK
INPUT
CLOCK
INPUT
AD951x
LVDS DRIVER
0
853
9-
020
Figure 50. Differential LVDS Sample Clock (Up to 4× Rated Sample Rate)
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK pin to ground with a 0.1 μF capacitor (see
OPTIONAL
100
0.1F
50
1
150
RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
VCC
1k
1k
CLOCK
INPUT
AD951x
CMOS DRIVER
08
53
9-
02
1
Figure 51. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
Input Clock Divider
The AD9649 contains an input clock divider with the ability
to divide the input clock by integer values of 1, 2, or 4.
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