參數(shù)資料
型號(hào)： AD9641-80KITZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 16/36頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9641
設(shè)計(jì)資源： AD9641 Gerber Files
AD9641 80KITZ BOM
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 1
位數(shù)： 14
采樣率（每秒）： 80M
數(shù)據(jù)接口： 串行，SPI?
輸入范圍： 1.4 ~ 2.1 Vpp
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9641
已供物品： 板
Data Sheet
AD9641
Rev. B | Page 23 of 36
Initial Frame Synchronization
The serial interface must synchronize to the frame boundaries
before data can be properly decoded. The JESD204A standard
has a synchronization routine to identify the frame boundary.
When the DSYNC pin is taken low for at least two clock cycles,
the AD9641 enters the code group synchronization mode. The
AD9641 transmits the K28.5 comma symbol until the receiver
achieves synchronization. The receiver should then deassert the
sync signal (take DSYNC high), and the AD9641 begins the initial
lane alignment sequence (when enabled through Address 0x60,
Bits[3:2]) and, subsequently, begins transmitting sample data. The
first non-K28.5 symbol corresponds to the first octet in a frame.
The DSYNC input can be driven either from a differential LVDS
source or by using a single-ended CMOS driver circuit. The
DSYNC input default to LVDS mode but can be set to CMOS
mode by setting Bit 4 in Address 0x61. If it is driven differen-
tially from an LVDS source, an external 100 Ω termination
resistor should be provided. If the DSYNC input is driven single
endedly, the CMOS signal should be connected to the DSYNC+
signal, and the DSYNC signal should be left disconnected.
Frame and Lane Alignment Monitoring and Correction
Frame alignment monitoring and correction is part of the
JESD204A specification. The 14-bit word requires two octets to
transmit all the data. The two octets (MSB and LSB), where
F = 2, make up a frame. During normal operating conditions,
frame alignment is monitored via alignment characters, which
are inserted under certain conditions at the end of a frame.
Table 11 summarizes the conditions for character insertion,
along with the expected characters under the various operation
modes. If lane synchronization is enabled, the replacement
character value depends on whether the octet is at the end of
a frame or at the end of a multiframe.
Based on the operating mode, the receiver can ensure that it is
still synchronized to the frame boundary by correctly receiving
the replace characters.
Digital Outputs and Timing
The AD9641 has differential digital outputs that power up
by default. The driver current is derived on-chip and sets the
output current at each output equal to a nominal 4 mA. Each
output presents a 100 Ω dynamic internal termination to reduce
unwanted reflections.
A 100 Ω differential termination resistor should be placed at each
receiver input to result in a nominal 400 mV peak-to-peak swing at
the receiver (see Figure 65). Alternatively, single-ended 50 Ω
termination can be used. When single-ended termination is
used, the termination voltage should be DRVDD/2; otherwise,
ac coupling capacitors can be used to terminate to any single-
ended voltage.
The AD9641 digital outputs can interface with custom ASICs and
FPGA receivers, providing superior switching performance in
noisy environments. Single point-to-point network topologies are
recommended with a single differential 100 Ω termination resistor
placed as close as possible to the receiver logic. The common
mode of the digital output automatically biases itself to half the
supply of the receiver (that is, the common-mode voltage is 0.9 V
for a receiver supply of 1.8 V) if dc-coupled connecting is used
100
DIFFERENTIAL
TRACE PAIR
DOUT + x
DRVDD
DOUT – x
VCM = DRVDD/2
OUTPUT SWING = 400mV p-p
RECEIVER
09
21
0-
0
47
Figure 65. AC-Coupled Digital Output Termination Example
100
OR
100
DIFFERENTIAL
TRACE PAIR
DOUT+x
DRVDD
VRXCM
DOUT–x
VCM = Rx VCM
OUTPUT SWING = 400mV p-p
0.1F
RECEIVER
0921
0-
048
Figure 66. DC-Coupled Digital Output Termination Example
For receiver logic that is not within the bounds of the DRVDD
supply, an ac-coupled connection should be used. Place a 0.1 μF
capacitor on each output pin and derive a 100 Ω differential
termination close to the receiver side.
If there is no far-end receiver termination or if there is poor
differential trace routing, timing errors may result. To avoid
such timing errors, it is recommended that the trace length be
less than 8 inches and that the differential output traces be close
together and at equal lengths.
Table 11. AD9641 JESD204A Frame Alignment Monitoring and Correction Replacement Characters
Scrambling
Lane
Synchronization
Character to Be Replaced
Last Octet in Multiframe
Replacement
Character
Off
On
Last octet in frame repeated from previous frame
No
K28.7 (0xFC)
Off
On
Last octet in frame repeated from previous frame
Yes
K28.3 (0x7C)
Off
Last octet in frame repeated from previous frame
Not applicable
K28.7 (0xFC)
On
Last octet in frame equals D28.7 (0xFC)
No
K28.7 (0xFC)
On
Last octet in frame equals D28.3 (0x7C)
Yes
K28.3 (0x7C)
On
Off
Last octet in frame equals D28.7 (0x7C)
Not applicable
K28.7 (0xFC)
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