參數(shù)資料
型號： AD9639BCPZRL-170
廠商： Analog Devices Inc
文件頁數(shù)： 25/36頁
文件大?。?/td> 0K
描述： IC ADC 12B 170MSPS QUAD 72LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 210M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 1.39W
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 72-LFCSP
包裝： 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型： 8 個(gè)單端，單極；4 個(gè)差分，單極
其它名稱： AD9639BCPZRL-170DKR
Data Sheet
AD9639
Rev. B | Page 31 of 36
MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map register table (Table 15) has eight
bit locations. The memory map is divided into three sections: the
chip configuration registers (Address 0x00 to Address 0x02),
the device index and transfer registers (Address 0x05 and
Address 0xFF), and the ADC function registers (Address 0x08
to Address 0x53).
The leftmost column of the memory map indicates the register
address; the default value is shown in the second rightmost
column. The Bit 7 column is the start of the default hexadecimal
value given. For example, Address 0x09, the clock register, has a
default value of 0x01, meaning that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0,
Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001
in binary. This setting is the default for the duty cycle stabilizer
in the on condition. By writing a 0 to Bit 0 of this address, fol-
lowed by 0x01 in the device update register (Address 0xFF[0],
the transfer bit), the duty cycle stabilizer is turned off. It is
important to follow each write sequence with a transfer bit to
update the SPI registers. For more information about this and
other functions, consult the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
RESERVED LOCATIONS
Undefined memory locations should not be written to except
when writing the default values suggested in this data sheet.
Blank cells in Table 15 should be considered reserved bits and
have a 0 written into their registers during power-up.
DEFAULT VALUES
When the AD9639 comes out of a reset, critical registers are
preloaded with default values. These values are indicated in
LOGIC LEVELS
In Table 15, “bit is set” is synonymous with “bit is set to Logic 1”
or “writing Logic 1 for the bit.” Similarly, “bit is cleared” is synon-
ymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.”
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