參數(shù)資料
型號(hào)： AD9639BCPZRL-170
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 21/36頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12B 170MSPS QUAD 72LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 210M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 1.39W
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 72-LFCSP
包裝： 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型： 8 個(gè)單端，單極；4 個(gè)差分，單極
其它名稱： AD9639BCPZRL-170DKR
AD9639
Data Sheet
Rev. B | Page 28 of 36
TEMPOUT Pin
The TEMPOUT pin can be used as a coarse temperature sensor
to monitor the internal die temperature of the device. This pin
typically has a 737 mV output with a clock rate of 210 MSPS
and a negative going temperature coefficient of 1.12 mV/°C.
The voltage response of this pin is characterized in Figure 61.
0.85
0.83
0.81
0.79
0.77
0.75
0.73
0.71
0.69
0.67
0.65
–40 –30 –20 –10
0
10
20
30
40
50
60
70
80
TEMPERATURE (°C)
TE
M
P
OU
T
P
IN
V
O
L
T
A
G
E
(
V
)
07
97
3-
0
55
Figure 61. TEMPOUT Pin Voltage vs. Temperature
RBIAS Pin
To set the internal core bias current of the ADC, place a resistor
(nominally equal to 10.0 kΩ) between ground and the RBIAS pin.
The resistor current is derived on chip and sets the AVDD current
of the ADC to a nominal 610 mA at 210 MSPS. Therefore, it is
imperative that a 1% or less tolerance on this resistor be used to
achieve consistent performance.
VCM x Pins
The common-mode output pins can be enabled through the SPI
to provide an external reference bias voltage of 1.4 V for driving
the VIN + x/VIN x analog inputs. The VCM x pins may be
required when connecting external devices, such as an amplifier
or transformer, to interface to the analog inputs.
RESET Pin
The RESET pin resets the datapath and sets all SPI registers to
their default values. To use this pin, the user must resynchronize
the digital outputs. This pin is only 1.8 V tolerant.
PDWN Pin
When asserted high, the PDWN pin turns off all ADC channels,
including the output drivers. This function can be changed to
a standby function (see Address 0x08 in Table 15). This feature
allows the user to place all channels into standby mode. The
output drivers transmit pseudorandom data until the outputs
are disabled using the output mode register (Address 0x14).
When the PDWN pin is asserted high, the AD9639 is placed into
power-down mode, shutting down the reference, reference buffer,
PLL, and biasing networks. In this state, the ADC typically
dissipates 3 mW. If any of the SPI features are changed before
the power-down feature is enabled, the chip continues to function
after PDWN is pulled low without requiring a reset. The AD9639
returns to normal operating mode when the PDWN pin is pulled
low. This pin is only 1.8 V tolerant.
SDO Pin
The SDO pin is for use in applications that require a 4-wire SPI
mode operation. For normal operation, it should be tied low to
AGND through a 10 kΩ resistor. Alternatively, the device pin
can be left open, and the 345 Ω internal pull-down resistor pulls
this pin low. This pin is only 1.8 V tolerant.
SDI/SDIO Pin
The SDI/SDIO pin is for use in applications that require either a
4- or 3-wire SPI mode operation. For normal operation, it should
be tied low to AGND through a 10 kΩ resistor. Alternatively,
the device pin can be left open, and the 30 kΩ internal pull-
down resistor pulls this pin low. This pin is only 1.8 V tolerant.
SCLK Pin
For normal operation, the SCLK pin should be tied to AGND
through a 10 kΩ resistor. Alternatively, the device pin can be left
open, and the 30 kΩ internal pull-down resistor pulls this pin
low. This pin is only 1.8 V tolerant.
CSB Pin
For normal operation, the CSB pin should be tied high to AVDD
through a 10 kΩ resistor. Alternatively, the device pin can be left
open, and the 26 kΩ internal pull-up resistor pulls this pin high.
Tying the CSB pin to AVDD causes all information on the SCLK
and SDI/SDIO pins to be ignored. Tying the CSB pin low causes
all information on the SDO and SDI/SDIO pins to be written to
the device. This feature allows the user to reduce the number of
traces to the device if necessary. This pin is only 1.8 V tolerant.
PGMx Pins
All PGMx pins are automatically initialized as synchronization
pins by default. These pins are used to lock the FPGA timing and
data capture during initial startup. These pins are respective to
each channel (PGM3 = Channel A, PGM2 = Channel B, and so
on). The sync (PGMx) pin should be pulled high until this pin
receives a low signal input from the receiver, during which time
the ADC outputs K28.5 comma symbols to indicate the frame
boundary. When the receiver finds the frame boundary, the
sync identification is deasserted low and the ADC outputs the
valid data on the next packet boundary.
When steady state operation for the device is achieved, these pins
can be assigned as a standby option using the PGM mode register
(Address 0x53 in Table 15). All other PGMx pins become global
synchronization pins. This pin is only 1.8 V tolerant.
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