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參數(shù)資料
| 型號： | AD9549ABCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 63/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 產(chǎn)品變化通告： | AD9549A Mask Change 22/Oct/2010 |
| 標準包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750MHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
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AD9549
Rev. D | Page 66 of 76
Register 0x030C—Control
Table 81.
Bits
Bit Name
Description
7
Enable REFA LOR
The REFA LOR limits are set up in Registers 0x031E to Register 0x031F.
6
Enable REFA OOL
The REFA OOL limits are set up in Register 0x0322 to Register 0x032B.
5
Enable REFB LOR
The REFB LOR limits are set up in Register 0x0320 to Register 0x0321.
4
Enable REFB OOL
The REFB OOL limits are set up in Register 0x032C to Register 0x0335.
[3:2]
Reserved
Reserved.
1
Enable phase lock detector
Register 0x0314 to Register 0x0318 must be set up to use this (see the Phase Lock Detection section).
0
Enable frequency lock detector
Register 0x0319 must be set up to use this. See the Frequency Lock Detection section.
Register 0x030D—Reserved
Register 0x030E—HFTW (Read Only)
Table 82.
Bits
Bit Name
Description
[7:0]
Average or instantaneous
FTW
These read-only registers are the output of FTW monitor. Average or instantaneous is determined by
holdover mode (see Bit 4, Register 0x01C0). These registers must be manually refreshed by
issuing an I/O update.
Register 0x030F—HFTW (Read Only) (Continued)
Table 83.
Bits
Bit Name
Description
[15:8]
Average or instantaneous
FTW
These read-only registers are the output of FTW monitor. Average or instantaneous is determined by
holdover mode (see Bit 4, Register 0x01C0). These registers must be manually refreshed by
issuing an I/O update.
Register 0x0310—HFTW (Read Only) (Continued)
Table 84.
Bits
Bit Name
Description
[23:16]
Average or instantaneous
FTW
These read-only registers are the output of FTW monitor. Average or instantaneous is determined by
holdover mode (see Bit 4, Register 0x01C0). These registers must be manually refreshed by
issuing an I/O update.
Register 0x0311—HFTW (Read Only) (Continued)
Table 85.
Bits
Bit Name
Description
[31:24]
Average or instantaneous
FTW
These read-only registers are the output of FTW monitor. Average or instantaneous is determined by
holdover mode (see Bit 4, Register 0x01C0). These registers must be manually refreshed by
issuing an I/O update.
Register 0x0312—HFTW (Read Only) (Continued)
Table 86.
Bits
Bit Name
Description
[39:32]
Average or instantaneous
FTW
These read-only registers are the output of FTW monitor. Average or instantaneous is determined by
holdover mode (see Bit 4, Register 0x01C0). These registers must be manually refreshed by
issuing an I/O update.
Register 0x0313—HFTW (Read Only) (Continued)
Table 87.
Bits
Bit Name
Description
[47:40]
Average or instantaneous
FTW
These read-only registers are the output of FTW monitor. Average or instantaneous is determined by
holdover mode (see Bit 4, Register 0x01C0). These registers must be manually refreshed by
issuing an I/O update.
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| AD9549ABCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9549APCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
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| AD9549BCPZ-REEL7 | 制造商:Analog Devices 功能描述:PLL CLOCK SYNTHESIZER SGL 64LFCSP EP - Tape and Reel |
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