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參數(shù)資料
| 型號(hào)： | AD9549ABCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 32/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 產(chǎn)品變化通告： | AD9549A Mask Change 22/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750MHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 776 (CN2011-ZH PDF) |
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AD9549
Rev. D | Page 38 of 76
The measurement error (ε) associated with the frequency
estimator depends on the choice of the measurement interval
parameter (K). These are related by
( )
1
floor
=
ρK
ε
With a specified fractional error (ε0), only those values of K
for which ε ≤ ε0 results in a frequency estimate that meets the
requirements. A plot of ε vs. K (for a given ρ) takes on the
general form that is shown in Figure 48.
ε BOUNDED
BY ENVELOPE
ε
0
1
216
ε < ε
0 FOR
SOME K
(K0 < K < K1)
ε > ε
0 FOR
ALL K < K0
ε < ε
0 FOR
ALL K > K1
KLO
K0
KHI
K1
K
06744-
048
Figure 48. Frequency Estimator ε vs. K
An iterative technique is necessary to determine the exact values
of K0 and K1. However, a closed form exists for a conservative
estimate of K0 (KLOW) and K1 (KHIGH).
+
=
0
LOW
ε
ρ
K
1
ceil
+
=
0
HIGH
ε
ρ
K
1
2
ceil
As an example, consider the following system conditions:
fS = 400 MHz
R = 8
fREF_IN = 155.52 MHz
ε0 = 0.00005 (that is, 50 ppm)
These conditions yield KMAX = 3185, which is the largest K value
that can be programmed without causing the frequency estimator
counter to overflow. With K = KMAX, Tmeas = 163.84 μs, and ε =
30.2 ppm, KMAX generally (but not always) yields the smallest
value of ε, but this comes at the cost of the largest measurement
time (Tmeas).
If the measurement time must be reduced, then KHIGH can be used
instead of KMAX. This yields KHIGH = 1945, Tmeas = 100.05 μs, and
ε = 39.4 ppm.
The measurement time can be further reduced (though
marginally) by using K1 instead of KHIGH. K1 is found by solving
the ε ≤ ε0 inequality iteratively. To do so, start with K = KHIGH
and decrement K successively while evaluating the inequality
for each value of K. Stop the process the first time that the
inequality is no longer satisfied and add 1 to the value of K
thus obtained. The result is the value of K1. For the preceding
example, K1 = 1912, Tmeas = 98.35 μs, and ε = 39.8 ppm.
If a further reduction of the measurement time is necessary,
K0 can be used. K0 is found in a manner similar to K1. Start with
K = KLOW and increment K successively while evaluating the
inequality for each value of K. Stop the process the first time that
the inequality is satisfied. The result is the value of K0. For the
preceding example, K0 = 1005, Tmeas = 51.70 μs, and ε = 49.0 ppm.
If external frequency division exists between the DAC output
and the FDBK_IN pins, the frequency estimator should not be
used because it will calculate the wrong initial frequency.
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| AD9549ABCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9549APCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9549BCPZ | 制造商:Analog Devices 功能描述: |
| AD9549BCPZ-REEL7 | 制造商:Analog Devices 功能描述:PLL CLOCK SYNTHESIZER SGL 64LFCSP EP - Tape and Reel |
| AD9549BCPZ-TR | 制造商:Analog Devices 功能描述:650MHZ DDS CLK GEN W/SYNCH REEL - Tape and Reel |
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