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參數(shù)資料
| 型號： | AD9549A/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 49/76頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9549A |
| 設計資源： | AD9549 Schematics AD9549 Gerber Files |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9549A |
| 主要屬性： | 8 kHz ~ 750 MHz 輸入 |
| 次要屬性： | 差分輸出 |
| 已供物品： | 板 |
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AD9549
Rev. D | Page 53 of 76
I/O REGISTER DESCRIPTIONS
SERIAL PORT CONFIGURATION (REGISTER 0x0000 TO REGISTER 0x0005)
Register 0x0000—Serial Configuration
Table 14.
Bits
Bit Name
Description
[7:4]
These bits are the mirror image of Bits[3:0].
3
Long instruction
Read-only. The AD9549 supports only long instructions.
2
Soft reset
Resets register map, except for Register 0x0000. Setting this bit forces a soft reset, meaning that S1 to S4
are not tristated, nor is their state read when this bit is cleared. The AD9549 assumes the values of S1 to S4
that were present during the last hard reset. This bit is not self-clearing, and all other registers are restored
to their default values after a soft reset.
1
LSB first
Sets bit order for serial port.
1 = LSB first.
0 = MSB first. I/O update must occur for MSB first to take effect.
0
SDO active
Enables SDO pin.
1 = SDO pin enabled (4-wire serial port mode).
0 = 3-wire mode.
Register 0x0001—Reserved
Register 0x0002 and Register 0x0003—Part ID (Read Only)
Register 0x0004—Serial Options
Table 15.
Bits
Bit Name
Description
0
Read buffer register
For buffered registers, serial port readback reads from actual (active) registers instead of the buffer.
1 = reads the buffered values that take effect during the next I/O update.
0 = reads values that are currently in effect.
Register 0x0005—Serial Options (Self-Clearing)
Table 16.
Bits
Bit Name
Description
0
Register update
Software access to the register update pin function. Writing a 1 to this bit is identical to performing an I/O
update.
POWER-DOWN AND RESET (REGISTER 0x0010 TO REGISTER 0x0013)
Register 0x0010—Power-Down and Enable
Power-up default is defined by the startup pins.
Table 17.
Bits
Bit Name
Description
7
PD HSTL driver
Power down HSTL output driver.
1 = HSTL driver powered down.
6
Enable CMOS driver
Power up CMOS output driver.
1 = CMOS driver on.
5
Enable output doubler
Power up output clock generator doubler. Output doubler must still be enabled in Register 0200.
4
PD SYSCLK PLL
System clock multiplier power-down.
1 = system clock multiplier powered down.
3
PD REFA
Power-down reference clock A input (and related circuits).
2
PD REFB
Power-down reference clock B input (and related circuits).
1
Full PD
Setting this bit is identical to activating the PD pin and puts all blocks (except serial port) into power-down
mode. SYSCLK is turned off.
0
Digital PD
Remove clock from most of digital section; leave serial port usable. In contrast to full PD, setting this bit
does not debias inputs, allowing for quick wake-up.
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