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參數(shù)資料
| 型號(hào)： | AD9549A/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 27/76頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9549A |
| 設(shè)計(jì)資源： | AD9549 Schematics AD9549 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9549A |
| 主要屬性： | 8 kHz ~ 750 MHz 輸入 |
| 次要屬性： | 差分輸出 |
| 已供物品： | 板 |
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AD9549
Rev. D | Page 33 of 76
FDBK_IN INPUTS
The feedback pins, FDBK_IN and FDBK_INB, serve as the input
to the feedback path of the digital PLL. Typically, these pins are
used to receive the signal generated by the DDS after it has been
band-limited by the external reconstruction filter.
A diagram of the FDBK input pins is provided in Figure 40,
which includes some of the internal components used to bias
the input circuitry. Note that the FDBK input pins are internally
biased to a dc level of ~1 V. Care should be taken to ensure that
any external connections do not disturb the dc bias because this
may significantly degrade performance.
06744-
040
15k
15k
~1pF
TO S-DIVIDER
AND CLOCK
OUTPUT SECTION
VSS
~1V
VSS
~2pF
+
FDBK_IN
FDBK_INB
Figure 40. Differential FDBK Inputs
REFERENCE INPUTS
Reference Clock Receiver
The reference clock receiver is the point at which the user
supplies the input clock signal that the synchronizer synthesizes
into an output clock. The clock receiver circuit is able to handle
a relatively broad range of input levels as well as frequencies
from 8 kHz up to 750 MHz.
Figure 41 is a diagram of the REFA and REFB input pins, which
includes some of the internal components used to bias the input
circuitry. Note that the REF input pins are internally biased by a
dc source, VB. Care should be taken to ensure that any external
connections do not disturb the dc bias because such a disturbance
may significantly degrade performance.
Note that support for redundant reference clocks is achieved by
using the two reference clock receivers (REFA and REFB).
06744-
041
8k
8k
~1pF
TO REFERENCE
MONITOR AND
SWITCHING LOGIC
VB
VSS
+
REFA_IN
(OR REFB_IN)
REFA_INB
(OR REFB_INB)
VDD
1pF
GND
Figure 41. Reference Inputs
To accommodate a variety of input signal conditions, the value
of VB is programmable via a pair of bits in the I/O register map.
Table 6. Setting of Input Bias Voltage (VB)
Reference Bias Level, Register 0x040F[1:0]
V
B
00 (default)
AVDD3 800 mV
01
AVDD3 400 mV
10
AVDD3 1600 mV
11
AVDD3 1200 mV
SYSCLK INPUTS
Functional Description
The SYSCLK pins are where an external time base is connected
to the AD9549 for generating the internal high frequency
system clock (fS).
The SYSCLK inputs can be operated in one of three modes:
SYSCLK PLL bypassed
SYSCLK PLL enabled with input signal generated externally
Crystal resonator with SYSCLK PLL enabled
A functional diagram of the system clock generator is shown in
06744-
042
1
0
1
0
1
0
BIPOLAR
EDGE
DETECTOR
2
WITH CRYSTAL
RESONATOR
2
1
0
2
SYSCLK
PLL
ENABLED
WITH EXTERNAL DRIVE
SYSCLK PLL BYPASSED
SYSCLK
PLL
MULTIPLIER
1
0
2× REFERENCE FREQUENCY DOUBLER
(I/O REGISTER BIT)
PD SYSCLK PLL
(I/O REGISTER BIT)
DAC
SAMPLE
CLOCK
LOOP_FILTER
SYSCLK
SYSCLKB
CLKMODESEL
2
Figure 42. System Clock Generator Block Diagram
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