參數(shù)資料
型號(hào)： AD9523BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 44/60頁
文件大?。?/td> 0K
描述： IC INTEGER-N CLCK GEN 72LFCSP
標(biāo)準(zhǔn)包裝： 400
類型： 時(shí)鐘/頻率發(fā)生器，扇出緩沖器（分配）
PLL： 是
主要目的： 以太網(wǎng)，光纖通道，SONET/SDH
輸入： CMOS
輸出： HSTL，LVCMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:14
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1GHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 72-LFCSP-VQ（10x10）
包裝： 帶卷 (TR)
配用： AD9523/PCBZ-ND - BOARD EVAL FOR AD9523
Data Sheet
AD9523
Rev. C | Page 49 of 60
Output PLL (PLL2) (Address 0x0F0 to Address 0x0F6)
Table 45. PLL2 Charge Pump Control
Table 46. PLL2 Feedback N Divider Control
Table 47. PLL2 Control
Address
Bits
Bit Name
Description
0x0F2
7
PLL2 lock detector power-down
Controls power-down of the PLL2 lock detector.
1: lock detector powered down.
0: lock detector active.
6
Reserved
Default = 0; value must remain 0.
5
Enable frequency doubler
Enables doubling of the PLL2 reference input frequency.
1: enabled.
0: disabled.
4
Enable SPI control of antibacklash
pulse width
Controls the functionality of Register 0x0F2, Bits[3:2]. Set the antibacklash pulse
width to the minimum setting. By setting Bit 4 to 1 from the default of 0, Bits[3:2]
consequently default to 00.
0 (default): device automatically controls the antibacklash period to high (equivalent to
Register 0x0F2, Bits[3:2] = 10).
1: antibacklash period defined by Register 0x0F2, Bits[3:2] (recommended setting).
[3:2]
Antibacklash pulse width control
Controls the PFD antibacklash period of PLL2.
00 (default): minimum (recommended setting).
01: low.
10: high.
11: maximum.
These bits are ineffective unless Register 0x0F2, Bit 4 = 1.
[1:0]
PLL2 charge pump mode
Controls the mode of the PLL2 charge pump.
00: tristate.
01: pump up.
10: pump down.
11 (default): normal.
Table 48. VCO Control
Address
Bits
Bit Name
Description
0x0F3
[7:5]
Reserved
Reserved.
4
Force release of distribution
sync when PLL2 is unlocked
0 (default): distribution is held in sync (static) until the output PLL locks. Then it is
automatically released from sync with all dividers synchronized.
1: overrides the PLL2 lock detector state; forces release of the distribution from sync.
3
Treat reference as valid
0 (default): uses the PLL1 VCXO indicator to determine when the reference clock to
the PLL2 is valid.
1: treats the reference clock as valid even if PLL1 does not consider it to be valid.
2
Force VCO to midpoint
frequency
Selects VCO control voltage functionality.
0 (default): normal VCO operation.
1: forces VCO control voltage to midscale.
Address
Bits
Bit Name
Description
0x0F0
[7:0]
PLL2 charge pump control
These bits set the magnitude of the PLL2 charge pump current. Granularity is ~3.5 μA
with a full-scale magnitude of ~900 μA.
Address
Bits
Bit Name
Description
0x0F1
[7:6]
A counter
A counter word.
[5:0]
B counter
B counter word.
Feedback Divider Constraints
A Counter (Bits[7:6])
B Counter (Bits[5:0])
Allowed N Division (4 × B + A)
A = 0 or A = 1
B = 4
16, 17
A = 0 to A = 2
B = 5
20, 21, 22
A = 0 to A = 2
B = 6
24, 25, 26
A = 0 to A = 3
B ≥ 7
28, 29 … continuous to 255
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