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參數(shù)資料
| 型號(hào)： | AD9245BCP-80 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 80 MSPS, 3 V A/D Converter |
| 中文描述： | 1-CH 14-BIT FLASH METHOD ADC, PARALLEL ACCESS, QCC32 |
| 封裝： | EXPOSED PAD, MO-220-VHHD-2, LFCSP-32 |
| 文件頁(yè)數(shù)： | 3/28頁(yè) |
| 文件大小： | 1510K |
| 代理商： | AD9245BCP-80 |
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AD9245
AD9245–DC SPECIFICATIONS
Table 1. AVDD = 3 V, DRVDD = 2.5 V, Sample Rate = 80 MSPS, 2 V p-p Differential Input, 1.0 V External Reference, unless
otherwise noted
Parameter
Temp
RESOLUTION
Full
ACCURACY
No Missing Codes
Full
Offset Error
1
Full
Gain Error
25°C
Gain Error
1
Full
Differential Nonlinearity (DNL)
2
Full
Integral Nonlinearity (INL)
2
Full
TEMPERATURE DRIFT
Offset Error
1
Full
Gain Error
Full
Gain Error
1
Full
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Full
Load Regulation @ 1.0 mA
25°C
Output Voltage Error (0.5 V Mode)
25°C
Load Regulation @ 0.5 mA
25°C
INPUT REFERRED NOISE
VREF = 0.5 V
25°C
VREF = 1.0 V
25°C
ANALOG INPUT
Input Span, VREF = 0.5 V
Full
Input Span, VREF = 1.0 V
Full
Input Capacitance
3
Full
REFERENCE INPUT RESISTANCE
Full
POWER SUPPLIES
Supply Voltage
AVDD
Full
DRVDD
Full
Supply Current
IAVDD
2
Full
IDRVDD
2
25°C
PSRR
25°C
POWER CONSUMPTION
Low Frequency Input
4
25°C
Standby Power
5
25°C
AD9245BCP
Typ
Guaranteed
±0.30
±0.28
±0.70
±0.5
±1.4
±10
±12
±17
±3
±2
±6
±1
1.86
1.17
1
2
7
7
3.0
2.5
122
9
±0.01
366
1.0
Test Level
VI
VI
VI
V
VI
VI
VI
V
V
V
VI
V
V
V
V
V
IV
IV
V
V
IV
IV
VI
V
V
V
V
Min
14
2.7
2.25
Max
±1.2
±4.16
±1.0
±5.15
±34
3.6
3.6
138
Unit
Bits
% FSR
% FSR
% FSR
LSB
LSB
ppm/°C
ppm/°C
ppm/°C
mV
mV
mV
mV
LSB rms
LSB rms
V p-p
V p-p
pF
k
V
V
mA
mA
% FSR
mW
mW
1
With a 1.0 V internal reference.
2
Measured at the maximum clock rate, f
IN
= 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to
4
Measured at AC Specification conditions without output drivers.
5
Standby power is measured with a dc input, CLK pin inactive (i.e., set to AVDD or AGND).
for the equivalent analog input structure.
Figure 4
Rev. B | Page 3 of 28
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