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| 型號： | AD9244BST-65 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 40/65 MSPS Monolithic A/D Converter |
| 中文描述： | 1-CH 14-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026-BBC, LQFP-48 |
| 文件頁數(shù)： | 15/36頁 |
| 文件大?。?/td> | 1845K |
| 代理商： | AD9244BST-65 |
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REV. A
AD9244
–15–
THEORY OF OPERATION
The AD9244 is a high performance, single-supply 14-bit ADC. In
addition to high dynamic range Nyquist sampling, it is designed for
excellent IF undersampling performance with an analog input as
high as 240 MHz.
The AD9244 uses a calibrated 10-stage pipeline architecture
with a patented wideband, input sample-and-hold amplifier
(SHA) implemented on a cost-effective CMOS process. Each stage
of the pipeline, excluding the last, consists of a low resolution flash
ADC along with a switched capacitor DAC and interstage residue
amplifier (MDAC). The MDAC amplifies the difference between
the reconstructed DAC output and the flash input for the next
stage in the pipeline. One bit of redundancy is used in each of the
stages to facilitate digital correction of flash errors. The last stage
simply consists of a flash ADC.
The pipeline architecture allows a greater throughput rate at the
expense of pipeline delay or latency. While the converter captures a
new input sample every clock cycle, it takes eight clock cycles
for the conversion to be fully processed and appear at the out-
put as illustrated in Figure 1. This latency is not a concern in
many applications. The digital output, together with the OTR
indicator, is latched into an output buffer to drive the output
pins. The output drivers of the AD9244 can be configured to
interface with 5 V or 3.3 V logic families.
The AD9244 has a duty clock stabilizer (DCS) that generates
its own internal falling edge to create an internal 50% duty cycle
clock, independent of the externally applied duty cycle. Control
of straight binary or twos complement output format is accom-
plished with the DFS pin.
The ADC samples the analog input on the rising edge of the
clock. While the clock is low, the input SHA is in sample mode.
When the clock transitions to a high logic level, the SHA goes
into the hold mode. System disturbances just prior to or imme-
diately after the rising edge of the clock and/or excessive clock
jitter may cause the SHA to acquire the wrong input value and
should be minimized.
ANALOG INPUT AND REFERENCE OVERVIEW
The differential input span of the AD9244 is equal to the potential
at the VREF pin. The VREF potential may be obtained from the
internal AD9244 reference or an external source.
In differential applications, the center point of the input span is
the common-mode level of the input signals. In single-ended
applications, the center point is the dc potential applied to one
input pin while the signal is applied to the opposite input pin.
Figures 3a to 3c show various system configurations.
REFT
REFB
VREF
SENSE
REFGND
AD9244
VIN+
VIN–
33
2.5V
1.5V
20pF
2V
10 F
0.1 F
0.1 F
0.1 F
0.1 F
10 F
33
2.5V
1.5V
50
+
+
Figure 3a. 2 V p-p Differential Input, Common-Mode
Voltage = 2 V
REFT
REFB
VREF
SENSE
REFGND
AD9244
VIN+
VIN–
33
20pF
2V
10 F
0.1 F
0.1 F
0.1 F
0.1 F
10 F
33
3.0V
1.0V
+
+
Figure 3b. 2 V p-p Single-Ended Input, Common-Mode
Voltage = 2 V
3.0V
2.5V
2.0V
REFT
REFB
VREF
SENSE
REFGND
AD9244
CML
VIN+
VIN–
33
20pF
2V
10 F
0.1 F
0.1 F
0.1 F
0.1 F
10 F
33
3.0V
2.0V
2.5V
0.1 F
50
+
+
Figure 3c. 2 V p-p Differential Input, Common-Mode
Voltage = 2.5 V
Figure 4 is a simplified model of the AD9244 analog input,
showing the relationship between the analog inputs, VIN+, VIN
–
,
and the reference voltage, VREF. Note that this is only a sym-
bolic model and that no actual negative voltages exist inside the
AD9244. Similar to the voltages applied to the top and bottom
of the resistor ladder in a flash ADC, the value VREF/2 defines
the minimum and maximum input voltages to the ADC core.
AD9244
14
ADC
CORE
+VREF/2
–VREF/2
VIN+
VIN–
V
CORE
+
–
Figure 4. Equivalent Analog Input of AD9244
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9244BSTRL-40 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 40/65 MSPS Monolithic A/D Converter |
| AD9244BSTRL-65 | 制造商:Analog Devices 功能描述:Single ADC Pipelined 65Msps 14-bit Parallel 48-Pin LQFP T/R |
| AD9244BSTZ40 | 制造商:Analog Devices 功能描述: |
| AD9244BSTZ-40 | 功能描述:IC ADC 14BIT 40MSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個(gè)單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD9244BSTZ-401 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 40 MSPS/65 MSPS A/D Converter |
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