參數(shù)資料
型號(hào): AD8352ACPZ-R7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 18/20頁(yè)
文件大?。?/td> 0K
描述: IC AMP RF/IF DIFF 2GHZ 16-LFCSP
產(chǎn)品培訓(xùn)模塊: Differential Circuit Design Techniques for Communication Applications
設(shè)計(jì)資源: Using AD8352 as an Ultralow Distortion Differential RF/IF Front End for High Speed ADCs (CN0046)
標(biāo)準(zhǔn)包裝: 1
放大器類(lèi)型: RF/IF 差分
電路數(shù): 1
輸出類(lèi)型: 差分
轉(zhuǎn)換速率: 8000 V/µs
-3db帶寬: 2.2GHz
電流 - 輸入偏壓: 75nA
電流 - 電源: 37mA
電壓 - 電源,單路/雙路(±): 3 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-VQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 16-LFCSP-VQ
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 550 (CN2011-ZH PDF)
其它名稱: AD8352ACPZ-R7DKR
AD8352
Rev. B | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
RDP
2
RGP
3
RGN
4
RDN
11 VOP
12 GND
10 VON
9GND
5
V
IN
6
G
N
D
7
G
N
D
8
V
C
15
E
N
B
16
V
IP
14
V
C
M
13
V
C
TOP VIEW
(Not to Scale)
AD8352
05
72
8-
00
3
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
RDP
Positive Distortion Adjust.
2
RGP
Positive Gain Adjust.
3
RGN
Negative Gain Adjust.
4
RDN
Negative Distortion Adjust.
5
VIN
Balanced Differential Input. This pin is biased to VCM, typically ac-coupled.
6, 7, 9, 12
GND
Ground. Connect this pin to low impedance GND.
8, 13
VCC
Positive Supply.
10
VON
Balanced Differential Output. This pin is biased to VCM, typically ac-coupled.
11
VOP
Balanced Differential Output. This pin is biased to VCM, typically ac-coupled.
14
VCM
Common-Mode Voltage. A voltage applied to this pin sets the common-mode voltage of the input and output.
Typically decoupled to ground with a 0.1 μF capacitor. With no reference applied, input and output common
mode floats to midsupply (VCC/2).
15
ENB
Enable. Apply positive voltage (1.3 V < ENB < VCC) to activate device.
16
VIP
Balanced Differential Input. This pin is biased to VCM, typically ac-coupled.
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