AD8150
Rev. A | Page 25 of 44
The resistor value current is given by the following expression:
OUT
SET
I
R
25
=
Example:
mA
2
.
16
kΩ
54
.
1
=
OUT
SET
I
for
R
The minimum set resistor is RSET,min = 1 kΩ, resulting in IOUT,max =
25 mA. The maximum set resistor is RSET,max = 5 kΩ, resulting in
IOUT,min = 5 mA. Nominal 800 mV output swings can be achieved
in a 50 Ω load using RSET = 1.56 kΩ (IOUT = 16.2 mA) or in a
doubly terminated 75 Ω load using RSET = 1.17 kΩ (IOUT =
21.3 mA).
To minimize stray capacitance and avoid the pickup of
unwanted signals, the external set resistor should be located
close to the REF pin. Bypassing the set resistor is not
recommended.
POWER SUPPLIES
There are several options for the power supply voltages for the
AD8150, because there are two separate sections of the chip that
require power supplies. These are the control logic and the high
speed data paths. The voltage levels of these supplies can vary,
depending on the system architecture.
Logic Supplies
The control (programming) logic is CMOS and is designed to
interface with any of the various standard single-ended logic
families (CMOS or TTL). Its supply voltage pins are VDD (Pin
170, logic positive) and VSS (Pin 152, logic ground). In all cases
the logic ground should be connected to the system digital
ground. VDD should be supplied at a voltage between 3.3 V and
5 V to match the supply voltage of the logic family that is used
to drive the logic inputs. VDD should be bypassed to ground
with a 0.1 μF ceramic capacitor. The absolute maximum voltage
from VDD to VSS is 5.5 V.
Data Path Supplies
The data path supplies have more options for their voltage
levels. The choices here will affect several other areas, such as
power dissipation, bypassing, and common-mode levels of the
inputs and outputs. The more positive voltage supply for the
data paths is VCC (Pins 41, 98, 149, and 171). The more negative
supply is VEE, which appears on many pins that will not be listed
here. The maximum allowable voltage across these supplies is
5.5 V.
The first choice in the data path power supplies is to decide
whether to run the device as ECL (emitter-coupled logic) or
PECL (positive ECL). For ECL operation, VCC will be at ground
potential, and VEE will be at a negative supply between 3.3 V
and 5 V. This will make the common-mode voltage of the
01074-038
VCC
VDD
VEE
VSS
DATA
PATHS
CONTROL
LOGIC
3V TO 5V
GND
0.1
μF
0.1
μF
(ONE FOR EVERY TWO VEE PINS)
AD8150
Figure 38. Power Supplies and Bypassing for ECL Operation
If the data paths are to be dc-coupled to other ECL logic devices
that run with ground as the most positive supply and a negative
voltage for VEE, then this is the proper way to run. However, if
the part is to be ac coupled, it is not necessary to have the
input/output common mode at the same level as the other
system circuits, but it will probably be more convenient to use
the same supply rails for all devices.
For PECL operation, VEE will be at ground potential, and VCC
will be a positive voltage from 3.3 V to 5 V. Thus, the common
mode of the inputs and outputs will be at a positive voltage.
These can then be dc coupled to other PECL operated devices.
If the data paths are ac coupled, then the common-mode levels
01074-039
DATA
PATHS
CONTROL
LOGIC
VCC
VDD
VEE
VSS
0.1
μF
0.1
μF
(ONE FOR EACH VCC PIN,
4 REQUIRED)
3V TO 5V
GND
AD8150
Figure 39. Power Supplies and Bypassing for PECL Operation