VDD = V
參數(shù)資料
型號(hào)： AD7939BSUZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 34/36頁(yè)
文件大小： 0K
描述： IC ADC 10BIT 8CH PARALL 32TQFP
標(biāo)準(zhǔn)包裝： 500
位數(shù)： 10
采樣率（每秒）： 1.5M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 13.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-TQFP
供應(yīng)商設(shè)備封裝： 32-TQFP（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個(gè)單端，單極；4 個(gè)差分，單極；4 個(gè)偽差分，單極；7 偽差分，單極
配用： EVAL-AD7939CBZ-ND - BOARD EVALUATION FOR AD7939CBZ
Data Sheet
AD7938/AD7939
Rev. C | Page 7 of 36
TIMING SPECIFICATIONS
VDD = VDRIVE = 2.7 V to 5.25 V, internal/external VREF = 2.5 V, unless otherwise noted; fCLKIN = 25.5 MHz, fSAMPLE = 1.5 MSPS; TA = TMIN to
TMAX, unless otherwise noted.
Table 4.
Limit at TMIN, TMAX
Parameter1
AD7938
AD7939
Unit
Description
fCLKIN2
700
kHz min
CLKIN frequency.
25.5
MHz max
tQUIET
30
ns min
Minimum time between end of read and start of next conversion; in other words, time
from when the data bus goes into three-state until the next falling edge of CONVST.
t1
10
ns min
CONVST pulse width.
t2
15
ns min
CONVST falling edge to CLKIN falling edge setup time.
t3
50
ns max
CLKIN falling edge to BUSY rising edge.
t4
0
ns min
CS to WR setup time.
t5
0
ns min
CS to WR hold time.
t6
10
ns min
WR pulse width.
t7
10
ns min
Data setup time before WR.
t8
10
ns min
Data hold after WR.
t9
10
ns min
New data valid before falling edge of BUSY.
t10
0
ns min
CS to RD setup time.
t11
0
ns min
CS to RD hold time.
t12
30
ns min
RD pulse width.
30
ns max
Data access time after RD.
3
ns min
Bus relinquish time after RD.
50
ns max
Bus relinquish time after RD.
t15
0
ns min
HBEN to RD setup time.
t16
0
ns min
HBEN to RD hold time.
t17
10
ns min
Minimum time between reads/writes.
t18
0
ns min
HBEN to WR setup time.
t19
10
ns min
HBEN to WR hold time.
t20
40
ns max
CLKIN falling edge to BUSY falling edge.
t21
15.7
ns min
CLKIN low pulse width.
t22
7.8
ns min
CLKIN high pulse width.
1
Sample tested during initial release to ensure compliance. All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of VDD) and timed from a voltage level of
1.6 V. All timing specifications given above are with a 25 pF load capacitance (see Figure 36, Figure 37, Figure 38, and Figure 39).
2
Minimum CLKIN for specified performance, with slower SCLK frequencies performance specifications apply typically.
3
The time required for the output to cross 0.4 V or 2.4 V.
4
t14 is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or
discharging the 25 pF capacitor. This means that the time, t14, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the
bus loading.
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