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參數資料
| 型號： | AD7939BSUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 18/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 8CH PARALL 32TQFP |
| 標準包裝： | 500 |
| 位數： | 10 |
| 采樣率（每秒）： | 1.5M |
| 數據接口： | 并聯 |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 13.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-TQFP |
| 供應商設備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數目和類型： | 8 個單端，單極；4 個差分，單極；4 個偽差分，單極；7 偽差分，單極 |
| 配用： | EVAL-AD7939CBZ-ND - BOARD EVALUATION FOR AD7939CBZ |
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Data Sheet
AD7938/AD7939
Rev. C | Page 25 of 36
PARALLEL INTERFACE
The AD7938/AD7939 have a flexible, high speed, parallel
interface. This interface is 12-bits (AD7938) or 10-bits
(AD7939) wide and is capable of operating in either word
(W/B tied high) or byte (W/B tied low) mode. The CONVST
signal is used to initiate conversions; when operating in
autoshutdown or autostandby mode, it is used to initiate
power-up.
A falling edge on the CONVST signal is used to initiate
conversions and it puts the ADC track-and-hold into track.
Once the CONVST signal goes low, the BUSY signal goes high
for the duration of the conversion. In between conversions,
CONVST must be brought high for a minimum time of t1. This
must happen after the 14th falling edge of CLKIN; otherwise, the
conversion is aborted and the track-and-hold goes back into track.
At the end of the conversion, BUSY goes low and can be used to
activate an interrupt service routine. The CS and RD lines are
then activated in parallel to read the 12- or 10-bits of conversion
data. When power supplies are first applied to the device, a
rising edge on CONVST is necessary to put the track-and-hold
into track. The acquisition time of 125 ns minimum must be
allowed before CONVST is brought low to initiate a conversion.
The ADC then goes into hold on the falling edge of CONVST
and back into track on the 13th rising edge of CLKIN after this
(see Figure 36). When operating the device in autoshutdown or
autostandby mode, where the ADC powers down at the end of
each conversion, a rising edge on the CONVST signal is used to
power up the device.
t2
t3
t20
t14
t11
t9
t13
t12
t10
tCONVERT
tACQUISITION
tQUIET
t1
12
3
4
5
12
13
14
B
A
DATA
OLD DATA
DB0 TO DB11
RD
CS
INTERNAL
TRACK/HOLD
BUSY
CLKIN
CONVST
THREE-STATE
WITH CS AND RD TIED LOW
03
71
5-
00
4
Figure 36. AD7938/AD7939 Parallel Interface—Conversion and Read Cycle Timing in Word Mode (W/B = 1)
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