參數(shù)資料
型號(hào)： AD7938BCP
廠商： ANALOG DEVICES INC
元件分類(lèi)： ADC
英文描述： 8-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer
中文描述： 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, QCC32
封裝： MO-220-VHHD-2, LFCSP-32
文件頁(yè)數(shù)： 29/32頁(yè)
文件大?。?/td> 1332K
代理商： AD7938BCP
Preliminary Technical Data
AD7938/AD7939
POWER VS. THROUGHPUT RATE
A big advantage of powering the ADC down after a conversion
is that the power consumption of the part is significantly
reduced at lower throughput rates. When using the different
power modes, the AD7938/AD7939 is only powered up for the
duration of the conversion. Therefore, the average power
consumption per cycle is significantly reduced. F
show plots of power versus throughput when
operating in auto-shutdown and auto-standby modes.
and
igure 43
Figure 43. Power vs. Throughput in Auto-Shutdown Mode
Figure 44
Figure 44. Power vs. Throughput in Auto-Standby Mode
MICROPROCESSOR INTERFACING
AD7938/AD7939 to ADSP-21xx Interface
Figure 45
shows the AD7938/AD7939 interfaced to the ADSP-
21xx series of DSPs as a memory mapped device. A single wait
state may be necessary to interface the AD7938/AD7939 to the
ADSP-21xx depending on the clock speed of the DSP. The wait
state can be programmed via the data memory wait state
control register of the ADSP-21xx (please see the ADSP-21xx
family User’s Manual for details). The following instruction
reads from the AD7938/AD7939
Figure 45. Interfacing to the ADSP-21xx
AD7938/AD7939 to ADSP-21065L Interface
Figure 46
shows a typical interface between the
AD7938/AD7939 and the ADSP-21065L SHARC processor.
This interface is an example of one of three DMA handshake
modes. The MS
x
control line is actually three memory select
lines. Internal ADDR
25-24
are decoded into MS
3-0
, these lines are
then asserted as chip selects. The DMAR
1
(DMA request 1) is
used in this setup as the interrupt to signal the end of
conversion. The rest of the interface is standard handshaking
operation.
MR = DM(ADC)
where ADC is the address of the AD7938/AD7939.
AD7938/
AD7939*
ADSP-21xx*
WR
RD
DB0 TO DB11
D0 TO D23
A0 TO A15
DMS
IRQ2
BUSY
CS
CONVST
OPTIONAL
WR
RD
*ADDITIONAL PINS OMITTED FOR CLARITY
ADDRESS BUS
DATA BUS
ADDRESS
DECODER
0
Figure 46. Interfacing to the ADSP-21065L
AD7938/AD7939 to TMS32020, TMS320C25, and
TMS320C5x Interface
Parallel interfaces between the AD7938/AD7939 and the
TMS32020, TMS320C25, and TMS320C5x family of DSPs are
shown in
. The memory mapped address chosen for
the AD7938/AD7939 should be chosen to fall in the I/O
memory space of the DSPs. The parallel interface on the
AD7938/AD7939 is fast enough to interface to the TMS32020
with no extra wait states. If high speed glue logic, such as 74AS
devices, are used to drive the RD and the WR lines when
interfacing to the TMS320C25, then again, no wait states are
necessary. However, if slower logic is used, data accesses may be
AD7938/
AD7939*
ADSP-21065L*
WR
DB0 TO DB11
D0 TO D31
ADDR
0
TO ADDR
23
MS
X
DMAR
1
BUSY
CS
CONVST
OPTIONAL
WR
RD
RD
*ADDITIONAL PINS REMOVED FOR CLARITY
ADDRESS BUS
ADDRESS BUS
DATA BUS
ADDRESS
LATCH
ADDRESS
DECODER
0
Figure 47
Rev. PrN | Page 29 of 32
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