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參數(shù)資料
| 型號： | AD7938BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 8-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer |
| 中文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, QCC32 |
| 封裝： | MO-220-VHHD-2, LFCSP-32 |
| 文件頁數(shù)： | 19/32頁 |
| 文件大?。?/td> | 1332K |
| 代理商： | AD7938BCP |
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Preliminary Technical Data
AD7938/AD7939
ANALOG INPUT STRUCTURE
Figure 23 shows the equivalent circuit of the analog input
structure of the AD7938/AD7939 in differential/pseudo
differential mode. In single-ended mode, V
IN
is internally tied
to AGND. The four diodes provide ESD protection for the
analog inputs. Care must be taken to ensure that the analog
input signals never exceed the supply rails by more than
300 mV. This causes these diodes to become forward-biased and
starts conducting into the substrate. These diodes can conduct
up to 10 mA without causing irreversible damage to the part.
0
100...000
011...111
1 LSB = V
REF
/4096 (AD7938)
1 LSB = V
REF
/1024 (AD7939)
1 LSB = 2
×
V
REF
/4096 (AD7938)
1 LSB = 2
×
V
REF
/1024 (AD7939)
–V
REF
+ 1 LSB
V
REF
+V
REF
– 1 LSB
A
100...001
100...010
011...110
000...001
000...000
111...111
The C1 capacitors, in Figure 23, are typically 4 pF and can
primarily be attributed to pin capacitance. The resistors are
lumped components made up of the on resistance of the
switches. The value of these resistors is typically about 100 .
The C2 capacitors are the ADC’s sampling capacitors and have a
capacitance of 16 pF typically.
Figure 21. AD7938/AD7939 Ideal Transfer Characteristic
with Twos Complement Output Coding
TYPICAL CONNECTION DIAGRAM
Figure 22
shows a typical connection diagram for the
AD7938/AD7939. The AGND and DGND pins are connected
together at the device for good noise suppression. The
V
REFIN
/V
REFOUT
pin is decoupled to AGND with a 0.47 μF
capacitor to avoid noise pickup if the internal reference is used.
Alternatively, V
REFIN
/V
REFOUT
can be connected to an external
reference source, and in this case, the reference pin should be
decoupled with a 0.1 μF capacitor. In both cases, the analog
input range can either be 0 V to V
REF
(RANGE bit = 0) or 0 V to
2 × V
REF
(RANGE bit = 1). The analog input configuration can
be either eight single-ended inputs, four differential pairs, four
pseudo-differential pairs, or seven pseudo-differential inputs
(see
). The V
DD
pin is connected to either a 3 V or 5 V
supply. The voltage applied to the V
DRIVE
input controls the
voltage of the digital interface and here, it is connected to the
same 3 V supply of the microprocessor to allow a 3 V logic
interface (see the D
section).
igital Inputs
Figure 22. Typical Connection Diagram
For ac applications, removing high frequency components from
the analog input signal is recommended by the use of an RC
low-pass filter on the relevant analog input pins. In applications
where harmonic distortion and signal-to-noise ratio are critical,
the analog input should be driven from a low impedance source.
Large source impedances significantly affect the ac performance
of the ADC. This may necessitate the use of an input buffer
amplifier. The choice of the op amp will be a function of the
particular application.
R1
C2
V
IN
+
V
DD
C1
D
D
0
R1
C2
V
IN
–
V
DD
C1
D
D
Table 9
0
0.1
μ
F
10
μ
F
3V/5V
SUPPLY
3V
SUPPLY
μ
C/
μ
P
AD7938/AD7939
0.1
μ
F
0.1
μ
F EXTERNAL V
REF
0.47
μ
F INTERNAL V
REF
0 TO V
REF
/
0 TO 2
×
V
REF
AGND
DGND
W/B
CLKIN
CS
RD
WR
V
DRIVE
V
IN
0
V
DD
V
REFIN
/V
REFOUT
V
IN
7
10
μ
F
2.5V
V
REF
CONVST
BUSY
DB0
DB11/DB9
Figure 23. Equivalent Analog Input Circuit,
Conversion Phase—Switches Open, Track Phase—Switches Closed
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance will depend on the amount of THD that can
be tolerated. The THD increases as the source impedance
increases and performance degrades. F
the THD versus the analog input signal frequency for different
source impedances for both V
DD
= 5 V and 3 V.
shows a graph of
igure 24
Rev. PrN | Page 19 of 32
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