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參數(shù)資料
| 型號： | AD7938BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 8-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer |
| 中文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, QCC32 |
| 封裝： | MO-220-VHHD-2, LFCSP-32 |
| 文件頁數(shù)： | 27/32頁 |
| 文件大?。?/td> | 1332K |
| 代理商： | AD7938BCP |
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Preliminary Technical Data
AD7938/AD7939
Writing Data to the AD7938/AD7939
With W/B tied logic high, a single write operation transfers the
full data-word on DB0 to DB11 to the control register on the
AD7938/AD7939. The DB8/HBEN pin assumes its DB8
function. Data written to the AD7938/AD7939 should be
provided on the DB0 to DB11 inputs with DB0 being the LSB of
the data-word. With W/B tied logic low, the AD7938/AD7939
requires two write operations to transfer a full 12-bit word.
DB8/HBEN assumes its HBEN function. Data written to the
AD7938/AD7939 should be provided on the DB0 to DB7
inputs. HBEN determines whether the byte written is high byte
or low byte data. The low byte of the data-word should be
written first with DB0 being the LSB of the full data-word. For
the high byte write, HBEN should be high and the data on the
DB0 input should be data bit 8 of the 12-bit word. In both word
and byte mode, a single write operation to the shadow register is
always sufficient since it is only 8-bits wide.
Figure 40
Figure 40. AD7938/AD7939 Parallel Interface—Write Cycle Timing for Word Mode Operation (W/B = 1)
shows the write cycle timing diagram of the
AD7938/AD7939. When operated in word mode, the HBEN
input does not exist and only the one write operation is required
to write the word of data to the device. Data should be provided
on DB0 to DB11. When operated in byte mode, the two write
cycles shown in F
are required to write the full data-
word to the AD7938/AD7939. In F
transfers the lower 8 bits of the data-word from DB0 to DB7,
and the second write transfers the upper 4 bits of the data-word.
When writing to the AD7938/AD7939, the top 4 bits in the high
byte must be 0s.
, the first write
igure 41
igure 41
Figure 41. AD7938/AD7939 Parallel Interface—Write Cycle Timing for Byte Mode Operation (W/B = 0)
The data is latched into the device on the rising edge of WR.
The data needs to be setup a time, t
7
, before the WR rising edge
and held for a time, t
8
, after the WR rising edge. The CS and WR
signals are gated internally. CS and WR may be tied together as
the timing specifications for t
4
and t
5
are 0 ns minimum
(assuming CS and RD have not already been tied together).
t
8
t
5
t
7
t
6
t
4
DATA
DB0 TO DB11
WR
CS
0
t
5
t
4
t
7
t
18
t
18
t
19
t
19
t
8
t
6
t
17
LOW BYTE
HIGH BYTE
DB0 TO DB11
HBEN/DB8
WR
CS
0
Rev. PrN | Page 27 of 32
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