參數(shù)資料
型號(hào)： AD7933BRU
廠商： ANALOG DEVICES INC
元件分類(lèi)： ADC
英文描述： 4-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer
中文描述： 4-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28
封裝： MO-153-AE, TSSOP-28
文件頁(yè)數(shù)： 24/32頁(yè)
文件大?。?/td> 1253K
代理商： AD7933BRU
AD7933/AD7934
Preliminary Technical Data
Digital Inputs
The digital inputs applied to the AD7933/AD7934 are not
limited by the maximum ratings that limit the analog inputs.
Instead, the digital inputs applied can go to 7 V and are not
restricted by the AV
DD
+ 0.3 V limit that is on the analog inputs.
PARALLEL INTERFACE
The AD7933/AD7934 have a flexible, high speed, parallel
interface. This interface is 12-bits (AD7934) or 10-bits
(AD7933) wide and is capable of operating in either word (W/B
tied high) or byte (W/B tied low) mode. The CONVST signal is
used to initiate conversions, and when operating in auto
shutdown or auto standby mode, it is used to power up the
ADC.
Another advantage of the digital inputs not being restricted by
the AV
DD
+ 0.3 V limit is the fact that power supply sequencing
issues are avoided. If any of these inputs are applied before AV
DD
,
then there is no risk of latch-up as there would be on the analog
inputs if a signal greater than 0.3 V was applied prior to AV
DD
.
V
DRIVE
Input
The AD7933/AD7934 has a V
DRIVE
feature. V
DRIVE
controls the
voltage at which the parallel interface operates. V
DRIVE
allows the
ADC to easily interface to 1.8 V, 3 V, and 5 V processors. V
DRIVE
of 1.8 V can only be used if V
DD
= 2.7 V to 3.6 V.
A falling edge on the CONVST signal is used to initiate
conversions, and it also puts the ADC track-and-hold into track.
Once the CONVST signal goes low, the BUSY signal goes high
for the duration of the conversion. In between conversions,
CONVST must be brought high for a minimum time of t
1
. This
must happen after the 14
th
rising edge of CLKIN; otherwise, the
conversion will be aborted and the track-and-hold will go back
into track. At the end of the conversion, BUSY goes low and can
be used to activate an interrupt service routine. The CS and RD
lines are then activated in parallel to read the 12 bits or 10 bits
of conversion data. When power supplies are first applied to the
device, a rising edge on CONVST puts the track-and-hold into
track. The acquisition time of 135 ns minimum must be allowed
before CONVST is brought low to initiate a conversion. The
ADC will then go into hold on the falling edge of CONVST and
back into track on the 13
th
rising edge of CLKIN after this (see
). When operating the device in auto shutdown or auto
standby mode, where the ADC powers down at the end of each
conversion, a rising edge on the CONVST signal is used to
power up the device.
For example, if the AD7933/AD7934 operated with an AV
DD
of
5 V and the V
DRIVE
pin could be powered from a 3 V supply, the
AD7933/AD7934 has better dynamic performance with an
AV
DD
of 5 V while still being able to interface to 3 V processors.
Care should be taken to ensure V
DRIVE
does not exceed AV
DD
by
more than 0.3 V (see
).
Table 4
Figure 37
Figure 37. AD7933/AD7934 Parallel Interface—Conversion and Read Cycle in Word Mode (W/B = 1)
t
2
t
3
t
20
t
14
t
11
t
9
t
13
t
12
t
10
t
CONVERT
t
AQUISITION
t
QUIET
t
1
1
2
3
4
12
13
14
B
A
DATA
DATA
OLD DATA
DB0 TO DB11
DB0 TO DB11
RD
CS
INTERNAL
TRACK/HOLD
BUSY
CLKIN
CONVST
THREE-STATE
THREE-STATE
0
WITH CS AND RD TIED LOW
Rev. PrG | Page 24 of 32
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