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參數(shù)資料
| 型號： | AD7933BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 4-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer |
| 中文描述： | 4-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | MO-153-AE, TSSOP-28 |
| 文件頁數(shù)： | 11/32頁 |
| 文件大?。?/td> | 1253K |
| 代理商： | AD7933BRU |
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AD7933/AD7934
Preliminary Technical Data
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.
Negative Gain Error Match
This is the difference in negative gain error between any two
channels.
Channel-to-Channel Isolation
It is a measure of the level of crosstalk between channels. It is
measured by applying a full-scale sine wave signal to the three
nonselected input channels and applying a 50 kHz signal to the
selected channel. The channel-to-channel isolation is defined as
the ratio of the power of the 50 kHz signal on the selected
channel to the power of the noise signal that appears in the FFT
of this channel.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 . . .000) to
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB
Power Supply Rejection Ratio (PSRR)
It is defined as the ratio of the power in the ADC output at full-
scale frequency,
f
, to the power of a 100 mV p-p sine wave
applied to the ADC V
DD
supply of frequency
f
S
. The frequency
of the input varies from 1 kHz to 1 MHz.
Offset Error Match
This is the difference in offset error between any two channels.
Gain Error
This is the deviation of the last code transition (111 . . .110) to
(111 . . . 111) from the ideal (i.e., V
REF
– 1 LSB) after the offset
error has been adjusted out.
PSRR
(dB) = 10log(
Pf
/
Pf
S
)
Pf
is the power at frequency
f
in the ADC output;
Pf
S
is the
power at frequency
f
S
in the ADC output.
Gain Error Match
This is the difference in gain error between any two channels.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns into track mode and the
end of conversion. The track-and-hold acquisition time is the
time required for the output of the track-and-hold amplifier to
reach its final value, within ±1/2 LSB, after the end of
conversion.
Zero-Code Error
This applies when using the twos complement output coding
option, in particular to the 2 × V
REF
input range with V
REF
to
+V
REF
biased about the V
REFIN
point. It is the deviation of the
midscale transition (all 0s to all 1s) from the ideal V
IN
voltage,
i.e., V
REF
.
Signal-to-(Noise + Distortion) Ratio (SINAD)
This is the measured ratio of signal-to-(noise + distortion) at
the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (f
S
/2), excluding dc. The ratio is
dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the
quantization noise. The theoretical signal-to-(noise +
distortion) ratio for an ideal N-bit converter with a sine wave
input is given by
Zero-Code Error Match
This is the difference in zero-code error between any two
channels.
Positive Gain Error
This applies when using the twos complement output coding
option, in particular to the 2 × V
REF
input range with
V
REF
to
+V
REF
biased about the V
REFIN
point. It is the deviation of the last
code transition (011. . .110) to (011 .. . 111) from the ideal (i.e.,
+V
REF
– 1 LSB) after the zero-code error has been adjusted out.
Signal-to-
(
Noise + Distortion
) = (6.02
N
+ 1.76) dB
Positive Gain Error Match
This is the difference in positive gain error between any two
channels.
Thus, for a 12-bit converter, this is 74 dB, and for a 10-bit
converter, this is 62 dB.
Negative Gain Error
This applies when using the twos complement output coding
option, in particular to the 2 × V
REF
input range with V
REF
to
+V
REF
biased about the V
REF
point. It is the deviation of the first
code transition (100 . . . 000) to (100 . . . 001) from the ideal (i.e.,
V
REFIN
+ 1 LSB) after the zero-code error has been adjusted
out.
Rev. PrG | Page 11 of 32
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| AD7933BRU-REEL | 功能描述:IC ADC 10BIT 4CH 1.5MSPS 28TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
| AD7933BRU-REEL7 | 功能描述:IC ADC 10BIT 4CH 1.5MSPS 28TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
| AD7933BRUZ | 功能描述:IC ADC 10BIT 4CH 1.5MSPS 28TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7933BRUZ-REEL7 | 功能描述:IC ADC 10BIT 4CH 1.5MSPS 28TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
| AD7934 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer |
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