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| 型號： | AD7933BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 4-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer |
| 中文描述： | 4-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | MO-153-AE, TSSOP-28 |
| 文件頁數(shù)： | 22/32頁 |
| 文件大?。?/td> | 1253K |
| 代理商： | AD7933BRU |
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AD7933/AD7934
Preliminary Technical Data
Pseudo-Differential Mode
The AD7933/AD7934 can have two pseudo-differential pairs by
setting Bits MODE0 and MODE1 in the control register to 1, 0,
respectively. V
IN
+ is connected to the signal source that must
have an amplitude of V
REF
to make use of the full dynamic range
of the part. ADC input is applied to the V
IN
pin. The voltage
applied to this input provides an offset from ground or a pseudo
ground for the V
IN
+ input. The benefit of pseudo-differential
inputs is that they separate the analog input signal ground from
the ADC’s ground allowing dc common-mode voltages to be
cancelled. Figure 32 shows a connection diagram for the
pseudo-differential mode.
POWER ON
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION
SET SEQ0 = SEQ1 = 0. SELECT THE DESIRED
CHANNEL TO CONVERT ON (ADD1 TO ADD0).
ISSUE CONVST PULSE TO INITIATE A CONVERSION
ON THE SELECTED CHANNEL.
INITIATE A READ CYCLE TO READ THE DATA
FROM THE SELECTED CHANNEL.
INITIATE A WRITE CYCLE TO SELECT THE NEXT
CHANNEL TO BE CONVERTED ON BY
CHANGING THE VALUES OF BITS ADD2 TO ADD0
IN THE CONTROL REGISTER. SEQ0 = SEQ1 = 0.
0
V
IN+
V
IN–
V
REF
AD7933/
AD7934*
*ADDITIONAL PINS OMITTED FOR CLARITY
0
V
REF
p-p
0.47
μ
F
DC INPUT
VOLTAGE
RANGE
±
100mV
Figure 32. Pseudo-Differential Mode Connection Diagram
ANALOG INPUT SELECTION
As shown in
configuration by setting the values in Bits MODE0 and MODE1
in the control register. Assuming the configuration is chosen,
there are two different ways of selecting the analog input to be
converted depending on the state of the SEQ0 and SEQ1 bits in
the control register.
Normal Multichannel Operation (SEQ0 = SEQ1 = 0)
Any one of four analog input channels or two pairs of channels
may be selected for conversion in any order by setting the SEQ0
and SEQ1 bits in the control register both to 0. The channel to
be converted is selected by writing to Bits ADD1 and ADD0 in
the control register to program the multiplexer prior to the
conversion. This mode of operation is of a normal multichannel
ADC where each data write selects the next channel for
conversion. F
shows a flow chart of this mode of
operation. The channel configurations are shown in
, users can set up their analog input
Table 9
Table 9
.
igure 33
Figure 33. Normal Multichannel Operation Flow Chart
Using the Sequencer: Consecutive Sequence (SEQ0 = 1,
SEQ1 = 1)
A sequence of consecutive channels can be converted beginning
with Channel 0 and ending with a final channel selected by
writing to Bits ADD1 and ADD0 in the control register. This is
done by setting the SEQ0 and SEQ1 bits in the control register
both to 1. Once the control register is written to set this mode
up, the next conversion is on Channel 0, then Channel 1, and so
on until the channel selected by the address bits, ADD1 and
ADD0, is reached. The ADC then returns to Channel 0 and
starts the sequence again. The WR input must be kept high to
ensure that the control register is not accidentally overwritten
and the sequence interrupted. This pattern continues until such
time as the AD7933/AD7934 is written to. F
flow chart of the consecutive sequence mode.
shows the
igure 34
Figure 34. Consecutive Sequence Mode Flow Chart
POWER ON
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT
AND OUTPUT CONFIGURATION SELECT
FINAL CHANNEL (ADD1 AND ADD0) IN
CONSECUTIVE SEQUENCE.
SET SEQ0 = 1 SEQ1 = 1.
CONTINUOUSLY CONVERT ON A CONSECUTIVE
SEQUENCE OF CHANNELS FROM CHANNEL 0
UP TO AND INCLUDING THE PREVIOUSLY
SELECTEWITH EACH CONVST PULSE.
0
REFERENCE SECTION
The AD7933/AD7934 can operate with either the on-chip
reference or an external reference. The internal reference is
selected by setting the REF bit in the internal control register to 1.
A block diagram of the internal reference circuitry is shown in
Figure 35. The internal reference circuitry includes an on-chip
2.5 V band gap reference and a reference buffer. When using the
internal reference, the V
REFIN
/V
REFOUT
pin should be decoupled to
AGND with a 0.47 μF capacitor. This internal reference not only
provides the reference for the analog-to-digital conversion, but it
also is used externally in the system. It is recommended that the
reference output is buffered using an external precision op amp
before applying it anywhere in the system.
Rev. PrG | Page 22 of 32
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