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| 型號(hào)： | AD7933 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | ADC |
| 英文描述： | 4-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer |
| 中文描述： | 4-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | TSSOP-28 |
| 文件頁(yè)數(shù)： | 7/32頁(yè) |
| 文件大?。?/td> | 1253K |
| 代理商： | AD7933 |
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Preliminary Technical Data
AD7933/AD7934
TIMING SPECIFICATIONS
1
V
DD
= V
DRIVE
=2.7 V to 5.25 V, Internal/External V
REF
= 2.5 V, unless otherwise noted, F
CLKIN
= 24 MHz, F
SAMPLE
= 1.5 MSPS; T
A
= T
MIN
to
T
MAX
, unless otherwise noted.
Table 3.
Limit at T
MIN
, T
MAX
Parameter AD7933
AD7934
Unit
Description
kHz
min
MHz
max
Minimum time between end of read and start of next conversion, i.e., time from when the
data bus goes into three-state until the next falling edge of CONVST.
t
1
10
10
ns min
CONVST Pulse Width.
t
2
20
20
ns min
CONVST Falling Edge to CLKIN Falling Edge Setup Time.
t
3
TBD
TBD
ns min
CLKIN Falling Edge to BUSY Rising Edge.
t
4
0
0
ns min
CS to WR Setup Time.
t
5
0
0
ns min
CS to WR Hold Time.
t
6
25
25
ns min
WR Pulse Width.
t
7
10
10
ns min
Data Setup Time before WR.
t
8
5
5
ns min
Data Hold after WR.
t
9
0.5 t
CLKIN
0.5 t
CLKIN
ns min
New Data Valid before Falling Edge of BUSY.
t
10
0
0
ns min
CS to RD Setup Time.
t
11
0
0
ns min
CS to RD Hold Time.
t
12
55
55
ns min
RD Pulse Width.
t
133
50
50
ns max
Data Access Time after RD.
t
144
5
5
ns min
Bus Relinquish Time after RD.
40
40
ns max
Bus Relinquish Time after RD.
t
15
15
15
ns min
HBEN to RD Setup Time.
t
16
5
5
ns min
HBEN to RD Hold Time.
t
17
10
10
ns min
Minimum Time between Reads/Writes.
t
18
0
0
ns min
HBEN to WR Setup Time.
t
19
5
5
ns min
HBEN to WR Hold Time.
t
20
TBD
TBD
ns min
CLKIN Falling Edge to BUSY Rising Edge.
f
CLKIN2
10
10
24
24
t
QUIET
10
10
ns min
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
All timing specifications given above are with a 25 pF load capacitance. See
,
,
, and
.
(W/ = 1) Figure 38 Figure 39
Figure 40
2
Mark/space ratio for CLKIN is 40/60 to 60/40.
3
The time required for the output to cross TBD.
4
t
14
is derived from the measured time taken by the data outputs to change 0.5 V. The measured number is then extrapolated back to remove the effects of charging or
discharging the 25 pF capacitor. This means that the time, t
14
, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the
bus loading.
Figure 37. AD7933/AD7934 Parallel Interface—Conversion and Read Cycle in Word Mode
Rev. PrG | Page 7 of 32
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