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參數(shù)資料
| 型號(hào)： | AD7877ACBZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 15/45頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CTRLR TOUCH SCREEN 25-WLCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 電阻 |
| 觸摸面板接口： | 4 線 |
| 輸入數(shù)/鍵： | 1 TSC |
| 分辨率（位）： | 12 b |
| 評(píng)估套件： | 可供 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 數(shù)據(jù)速率/采樣率 (SPS，BPS)： | 125k |
| 電壓基準(zhǔn)： | 外部，內(nèi)部 |
| 電源電壓： | 2.7 V ~ 5.25 V |
| 電流 - 電源： | 1µA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 25-UFBGA，WLCSP |
| 供應(yīng)商設(shè)備封裝： | 25-WLCSP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁(yè)面： | 779 (CN2011-ZH PDF) |
| 配用： | EVAL-AD7877EBZ-ND - BOARD EVALUATION FOR AD7877 |
| 其它名稱： | AD7877ACBZ-REEL7DKR |
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Data Sheet
AD7877
Rev. D | Page 21 of 44
Table 6. Codes for Selecting Input Channel and Normal or Ratiometric Conversion
Channel
SER/DFR
CHADD(3:0)
Analog Input
X Switches
Y Switches
+REF
REF
0
0 0 0 0
X+ (Y position)
Off
On
Y+
Y
1
0
0 0 0 1
Y+ (X position)
On
Off
X+
X
2
0
0 0 1 0
Y (Z2)
X+ off, X on
Y+ on, Y off
Y+
X
3
0
0 01 1
AUX1
Off
VREF
GND
4
0
0 1 00
AUX2
Off
VREF
GND
5
0
0 1 0 1
AUX3
Off
VREF
GND
6
0
0 1 1 0
BAT1
Off
VREF
GND
7
0
0 1 1 1
BAT2
Off
VREF
GND
8
0
1 0 0 0
TEMP1
Off
VREF
GND
9
0
1 0 0 1
TEMP2
Off
VREF
GND
10
0
1 0 1 0
X+ (Z1)
X+ OFF, X ON
Y+ on Y off
Y+
X
-
0
1 0 1 1
Invalid address
-
0
1 1 0 0
Invalid address
-
0
1 1 0 1
Invalid address
-
0
1 1 1 0
Invalid address
-
0
1 1 1 1
Invalid address
0
1
0 0 0 0
X+ (Y position)
Off
On
VREF
GND
1
0 0 0 1
Y+ (X position)
On
Off
VREF
GND
2
1
0 0 1 0
Y (Z2)
X+ off, X on
Y+ on, Y off
VREF
GND
3
1
0 0 1 1
AUX1
Off
VREF
GND
4
1
0 1 0 0
AUX2
Off
VREF
GND
5
1
0 1 0 1
AUX3
Off
VREF
GND
6
1
0 1 1 0
BAT1
Off
VREF
GND
7
1
0 1 1 1
BAT2
Off
VREF
GND
8
1
1 0 0 0
TEMP1
Off
VREF
GND
9
1
1 0 0 1
TEMP2
Off
VREF
GND
10
1
1 0 1 0
X+ (Z1)
X+ off, X on
Y+ on, Y off
VREF
GND
-
1
10 1 1
Invalid address
-
1
1 1 0 0
Invalid address
-
1
1 1 0 1
Invalid address
-
1
1 1 1 0
Invalid address
-
1
1 1 1 1
Invalid address
CONTROL REGISTER 2
Timer (Control Register 2, Bits[1:0])
The TMR bits in Control Register 2 enable the ADC to
repeatedly perform a conversion or conversion sequence either
once only or at intervals of 512 s, 1.024 ms, or 8.19 ms. In slave
mode, the timer starts as soon as the conversion sequence is
finished. In master mode, the timer starts at the end of a
conversion sequence only if the screen remains touched. If the
touch is released at any stage, then the timer stops and, the next
time the screen is touched, a conversion sequence begins
immediately.
Table 7. Control Register 2 Timer Selection
TMR1
TMR0
Function
0
Convert only once (default)
0
1
Every 1024 clocks (512 s)
1
0
Every 2048 clocks (1.024 ms)
1
Every 16,384 clocks (8.19 ms)
Int/Ext Reference (Control Register 2, Bit[2])
If the REF bit in Control Register 2 is 0 (default value), the
internal reference is selected. Buffer any connection made to
VREF while the internal reference is selected (for example, to
supply a reference to other circuits). An external power supply
should not be connected to this pin while REF is equal to 0,
because it might overdrive the internal reference. Because the
internal reference is 2.5 V, it operates only with supply voltages
down to 2.7 V. Below this value, use an external reference.
If the REF bit is 1, the VREF pin becomes an input and the
internal reference is powered down. This overrides any setting
of the PM bits with regard to the reference. An external
reference can then be applied to the REF pin.
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