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參數(shù)資料
| 型號： | AD7863 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Simultaneous Sampling Dual 175 kSPS 14-Bit ADC(同時采樣175kSPS14位雙A/D轉(zhuǎn)換器) |
| 中文描述： | 雙同步采樣175 kSPS的14位ADC（同時采樣175kSPS14位雙的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 9/18頁 |
| 文件大?。?/td> | 291K |
| 代理商： | AD7863 |
AD7863
–9–
REV. 0
CIRCUIT DESCRIPTION
Analog Input Section
The AD7863 is offered as three part types: the AD7863-10,
which handles a
±
10 V input voltage range, the AD7863-3,
which handles input voltage range
±
2.5 V and the AD7863-2,
which handles a 0V to +2.5V input voltage range.
2k
V
+2.5V
REFERENCE
MUX
R2
R1
R3
TO ADC
REFERENCE
CIRCUITRY
TO INTERNAL
COMPARATOR
TRACK/
HOLD
V
REF
V
AX
AGND
AD7863-10/AD7863-3
Figure 3. AD7863-10/-3 Analog Input Structure
Figure 3 shows the analog input section for the AD7863-10 and
AD7863-3. The analog input range of the AD7863-10 is
±
10 V
into an input resistance of typically 9 k
. The analog input
range of the AD7863-3 is
±
2.5 V into an input resistance of
typically 3 k
. This input is benign, with no dynamic charging
currents as the resistor stage is followed by a high input imped-
ance stage of the track/hold amplifier. For the AD7863-10, R1
= 8 k
, R2 = 2 k
and R3 = 2 k
. For the AD7863-3, R1 = R2
= 2 k
and R3 is open circuit.
For the AD7863-10 and AD7863-3, the designed code transi-
tions occur on successive integer LSB values (i.e., 1 LSB, 2 LSBs,
3 LSBs . . .). Output coding is twos complement binary with
1 LSB = FS/16384. The ideal input/output transfer function for
the AD7863-10 and AD7863-3 is shown in Table I.
Table I. Ideal Input/Output Code Table for the AD7863-10/-3
Digital Output
Code Transition
Analog Input
l
+FSR/2 – 1 LSB
2
+FSR/2 – 2 LSBs
+FSR/2 – 3 LSBs
GND + 1 LSB
GND
GND – 1 LSB
–FSR/2 + 3 LSBs
–FSR/2 + 2 LSBs
–FSR/2 + 1 LSB
011 . . . 110 to 011 . . . 111
011 . . . 101 to 011 . . . 110
011 . . . 100 to 011 . . . 101
000 . . . 000 to 000 . . . 001
111 . . . 111 to 000 . . . 000
111 . . . 110 to 111 . . . 111
100 . . . 010 to 100 . . . 011
100 . . . 001 to 100 . . . 010
100 . . . 000 to 100 . . . 001
NOTES
1
FSR is full-scale range = 20 V (AD7863-10) and = 5 V (AD7863-3) with
REF IN = +2.5 V.
2
1 LSB = FSR/16384 = 1.22 mV (AD7863-10) and 0.3 mV (AD7863-3) with
REF IN = +2.5 V.
The analog input section for the AD7863-2 contains no biasing
resistors and the V
AX/BX
pin drives the input directly to the
multiplexer and track/hold amplifier circuitry. The analog input
range is 0 V to +2.5 V into a high impedance stage with an
input current of less than 100nA. This input is benign, with no
dynamic charging currents. Once again, the designed code tran-
sitions occur on successive integer LSB values. Output coding is
straight (natural) binary with 1 LSB = FS/16384 = 2.5 V/16384
= 0.15 mV. Table II shows the ideal input/output transfer func-
tion for the AD7863-2.
Table II. Ideal Input/Output Code Table for the AD7863-2
Digital Output
Code Transition
Analog Input
1
+FSR – 1 LSB
2
+FSR – 2 LSB
+FSR – 3 LSB
111 . . . 110 to 111 . . . 111
111 . . . 101 to 111 . . . 110
111 . . . 100 to 111 . . . 101
GND + 3 LSB
GND + 2 LSB
GND + 1 LSB
000 . . . 010 to 000 . . . 011
000 . . . 001 to 000 . . . 010
000 . . . 000 to 000 . . . 001
NOTES
1
FSR is Full-Scale Range and is 2.5 V for AD7863-2 with V
REF
= +2.5 V.
2
1 LSB = FSR/16384 and is 0.15 mV for AD7863-2 with V
REF
= +2.5 V.
OFFSET AND FULL-SCALE ADJUSTMENT
In most Digital Signal Processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale error effect is linear and does not cause
problems as long as the input signal is within the full dynamic
range of the ADC. Invariably, some applications will require
that the input signal span the full analog input dynamic range.
In such applications, offset and full-scale error will have to be
adjusted to zero.
Figure 4 shows a typical circuit that can be used to adjust the
offset and full-scale errors on the AD7863 (V
A1
on the AD7863-
10 version is shown for example purposes only). Where adjust-
ment is required, offset error must be adjusted before full-scale
error. This is achieved by trimming the offset of the op amp
driving the analog input of the AD7863 while the input voltage is
1/2 LSB below analog ground. The trim procedure is as follows:
apply a voltage of –0.61 mV (–1/2 LSB) at V
A1
in Figure 4 and
adjust the op amp offset voltage until the ADC output code
flickers between 11 1111 1111 1111 and 00 0000 0000 0000.
R2
500
V
*ADDITIONAL PINS OMITTED FOR CLARITY
V
AX
AGND
AD7863*
R1
10k
V
R4
10k
V
R5
10k
V
R3
10k
V
V1
INPUT RANGE =
6
10V
Figure 4. Full-Scale Adjust Circuit
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| AD7863AR-10 | 功能描述:IC ADC 14BIT DUAL 2CH 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7863AR-10REEL | 功能描述:IC ADC 14BIT DUAL 2CH 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7863AR-10REEL7 | 制造商:Analog Devices 功能描述:ADC Dual SAR 175ksps 14-bit Parallel 28-Pin SOIC W T/R |
| AD7863AR-2 | 功能描述:IC ADC 14BIT DUAL 2CH 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
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