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| 型號(hào)： | AD7863 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Simultaneous Sampling Dual 175 kSPS 14-Bit ADC(同時(shí)采樣175kSPS14位雙A/D轉(zhuǎn)換器) |
| 中文描述： | 雙同步采樣175 kSPS的14位ADC（同時(shí)采樣175kSPS14位雙的A / D轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 10/18頁(yè) |
| 文件大小： | 291K |
| 代理商： | AD7863 |
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AD7863
–10–
REV. 0
Gain error can be adjusted at either the first code transition (ADC
negative full scale) or the last code transition (ADC positive full
scale). The trim procedures for both cases are as follows:
Positive Full-Scale Adjust (-10 Version)
Apply a voltage of +9.9927 V (FS/2 – 1 LSBs) at V
A1
. Adjust R2
until the ADC output code flickers between 01 1111 1111 1110
and 01 1111 1111 1111.
Negative Full-Scale Adjust (-10 Version)
Apply a voltage of –9.9976 V (–FS + 1 LSB) at V
A1
and adjust
R2 until the ADC output code flickers between 10 0000 0000
0000 and 10 0000 0000 0001.
An alternative scheme for adjusting full-scale error in systems
that use an external reference is to adjust the voltage at the V
REF
pin until the full-scale error for any of the channels is adjusted
out. The good full-scale matching of the channels will ensure
small full-scale errors on the other channels.
TIMING AND CONTROL
Figure 5a shows the timing and control sequence required to
obtain optimum performance (Mode 1) from the AD7863. In
the sequence shown, a conversion is initiated on the falling edge
of
CONVST
. This places both track/holds into hold simulta-
neously and new data from this conversion is available in the
output register of the AD7863 5.2
μ
s later. The BUSY signal
indicates the end of conversion and at this time the conversion
results for both channels are available to be read. A second
conversion is then initiated. If the multiplexer select A0 is low,
the first and second read pulses after the first conversion ac-
cesses the result from Channel A (V
A1
and V
A2
respectively).
The third and fourth read pulses, after the second conversion
and A0 high, accesses the result from Channel B (V
B1
and V
B2
respectively). A0’s state can be changed any time after the
CONVST
goes high, i.e., track/holds into hold and 500 ns prior
to the next falling edge of
CONVST
. Data is read from the part
via a 14-bit parallel data bus with standard
CS
and
RD
signal,
i.e., the read operation consists of a negative going pulse on the
CS
pin combined with two negative going pulses on the
RD
pin
(while the
CS
is low), accessing the two 14-bit results. Once the
read operation has taken place, a further 400ns should be
allowed before the next falling edge of
CONVST
to optimize
the settling of the track/hold amplifier before the next conver-
sion is initiated. The achievable throughput rate for the part is
5.2
μ
s (conversion time) plus 100 ns (read time) plus 0.4
μ
s
(quiet time). This results in a minimum throughput time of
5.7
μ
s (equivalent to a throughput rate of 175 kHz).
Read Options
Apart from the Read Operation described above and displayed
in Figure 5a, other
CS
and
RD
combinations can result in dif-
ferent channels/inputs being read in different combinations.
Suitable combinations are shown in Figures 5b through 5d.
CS
RD
DATA
V
A1
V
A2
Figure 5b. Read Option A (A0 Is Low)
CS
RD
DATA
V
A1
V
A2
V
A1
Figure 5c. Read Option B (A0 Is Low)
t
3
t
5
t
4
V
A1
V
A2
V
B1
V
B2
CONVST
BUSY
A0
CS
RD
DATA
t
1
t
7
t
2
t
6
t
CONV
= 5.2
m
s
t
ACQ
t
8
Figure 5a. Mode 1 Timing Operation Diagram for High Sampling Performance
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|---|---|
| AD7863AR-10 | 功能描述:IC ADC 14BIT DUAL 2CH 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD7863AR-10REEL | 功能描述:IC ADC 14BIT DUAL 2CH 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
| AD7863AR-10REEL7 | 制造商:Analog Devices 功能描述:ADC Dual SAR 175ksps 14-bit Parallel 28-Pin SOIC W T/R |
| AD7863AR-2 | 功能描述:IC ADC 14BIT DUAL 2CH 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| AD7863AR-2REEL | 制造商:Analog Devices 功能描述:ADC Dual SAR 175ksps 14-bit Parallel 28-Pin SOIC W T/R |
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