參數(shù)資料
型號(hào)： AD7851KRZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 33/36頁(yè)
文件大?。?/td> 0K
描述： IC ADC 14BIT SRL 333KSPS 24-SOIC
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 14
采樣率（每秒）： 333k
數(shù)據(jù)接口： 8051，QSPI?，串行，SPI? µP
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 89.25mW
電壓電源： 模擬和數(shù)字
工作溫度： 0°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 24-SOIC W
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 1 個(gè)偽差分，單極；1 個(gè)偽差分，雙極
AD7851
–6–
REV. B
TYPICAL TIMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams.
Figure 2 shows the reading and writing after conversion in
Interface Modes 2 and 3. To attain the maximum sample rate of
285 kHz in Interface Modes 2 and 3, reading and writing must
be performed during conversion. Figure 3 shows the timing dia-
gram for Interface Modes 4 and 5 with sample rate of 285 kHz.
At least a 330 ns acquisition time must be allowed (the time
from the falling edge of BUSY to the next rising edge of
CONVST) before the next conversion begins to ensure that the
part is settled to the 14-bit level. If the user does not want to
provide the
CONVST signal, the conversion can be initiated in
software by writing to the control register.
1.6mA
2.1V
200A
CL
50pF
TO
OUTPUT
PIN
IOL
IOH
Figure 1. Load Circuit for Digital Output Timing
Specifications
DB15
DB0
DB11
POLARITY PIN LOGIC HIGH
SYNC (I/P)
SCLK (I/P)
t
3
BUSY (O/P)
CONVST (I/P)
t
2
t
5
t
11
t
6
t
9
t
10
15
6
16
t
12
DOUT (O/P)
DB0
DB11
t
8
DIN (I/P)
THREE-STATE
DB15
t
CONVERT
t
CONVERT = 3.25s MAX, t1 = 100ns MIN,
t
5 = 30ns MAX, t7 = 30ns MIN
t
1
t
6
t
7
Figure 2. Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3)
POLARITY PIN LOGIC HIGH
SYNC ( O/P)
SCLK (O/P)
t
4
BUSY (O/P)
CONVST (I/P)
t
2
t
5
t
11
t
12
t
9
t
10
15
6
16
DOUT (O/P)
DB0
DB11
t
8
DIN (I/P)
DB15
DB0
THREE-STATE
DB11
THREE-STATE
DB15
t
CONVERT
t
CONVERT = 3.25s MAX, t1 = 100ns MIN,
t
5 = 30ns MAX, t7 = 30ns MIN
t
1
t
6
t
7
Figure 3. Timing Diagram (Typical Read and Write Operation for Interface Modes 4, 5)
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